Honeywell International Inc.

Honeywell G.m.b.h.

Devesh Bhatt

Kirk A Schloegel

David V Oglesby

Stephen Otis Hickman

Gabor Madl

Brendan Hall

Larry James Yount

Timothy D Mahoney

Richard F Hess

Arvind Easwaran

Steve Hickman

Todd Charles Steeves

Michael O Schroeder

Scot E Griffiths

Eric Engstrom

Philip E Rose

John Teager

William M McMahon

Manish Patodi

Kuntal Chakraborty

Kirk Schloegel

A method for automated error detection and verification of software comprises providing a model of the software, the model including one or more model inputs and one or more model outputs, and a plurality of blocks embedded within the model each with an associated block type, the block types each having a plurality of associated block-level requirements. The method further comprises topologically propagating from the model inputs, a range of signal values or variable values, and error bounds, across computational semantics of all the blocks to the model outputs. Each behavior pivot value for a given block is identified and examined to determine if modifying or extending the propagated range by the error bound will or may cause a signal value to fall on either side of the behavioral pivot value. All occurrences of the signal value that will or may fall on either side of the behavioral pivot value are reported.

Method for automated error detection and verification of software

Systems and methods for verifying model equivalence are provided. In one implementation, a system includes: a memory device that stores a reference model (RM) and comparison model (CM), wherein the CM and the RM are constrained by a set of rules; and a processing unit that generates a reference model representation (RMR) from the RM and stores the RMR on the memory device; the processing unit further generates a comparison model representation (CMR) from the comparison model (CM) and stores the CMR on the memory device, wherein the processing unit further to: verifies that the CMR compatibly implements the RMR; verifies that a CM data flow diagram derived from the CMR compatibly implements a RM data flow diagram derived from the RMR; and verifies that every CM semantic unit implements a behavior that corresponds to a RM semantic unit and every RM semantic unit is accounted for in the CM.

Systems and methods for verifying model equivalence

A system for verifying that a comparison model having folded expressions matches a reference model includes at least one memory device that stores a reference model and a comparison model, wherein the comparison model was previously generated based on the reference model. The reference model adheres to a first set of syntax and semantics, wherein the reference model includes a plurality of first expressions, each of the first expressions including a first operator and a first operand. The comparison model adheres to a second set of syntax and semantics, wherein the comparison model includes a second expression, the second expression including a second operator and a second operand. The system further includes a processing unit configured to match the second expression with the plurality of first expressions.

Systems and methods for verifying expression folding

Embodiments of the present subject matter can enable the analysis of signal value errors for system models. In an example, signal value errors can be propagated through the functional blocks of a system model to analyze possible effects as the signal value errors impact incident functional blocks. This propagation of the errors can be applicable to many models of computation including avionics models, synchronous data flow, and Kahn process networks.

Error propagation in a system model

Systems and methods for type and range propagation through data flow models are provided. In one embodiment, a test generating system for processing data flow diagrams, the system comprises: a processor programmed to perform a test generation process; and at least one memory device coupled to the processor, the at least one memory device including a data flow diagram. The test generation process computes range information and data type information for outputs of one or more functional blocks defined by the data flow diagram by applying transformations to input range information for inputs of each of the one or more functional blocks. The transformations are at least in part performed by applying specific mathematical and functional effects that are pre-defined for each of the one or more functional blocks based on block type.

Type and range propagation through data-flow models

A code generation system comprises a model analyzer configured to identify data dependencies in a data flow diagram that describes functional behavior of an application, wherein the model analyzer is further configured to compute a data and computation map based on the data dependencies and to compute one or more implementation constraints; a model partitioner configured to compute one or more partition boundaries based on the data and computation map and the one or more implementation constraints; and a code generator configured to generate parallelized code based on the data flow diagram, the one or more implementation constraints, and the one or more partition boundaries, wherein the code generator is configured to map the code corresponding to each partition defined by the one or more partition boundaries to one of a plurality of cores of a multi-core processor, and to generate inter-core communication code for at least one line of the data and computation map crossed by the one or more partition boundaries.

Auto-generation of concurrent code for multi-core applications

A test generator and methods for generating tests from a hybrid diagram are provided. A hybrid diagram is a diagram that primarily uses one higher-level semantic notation with portions utilizing one or more secondary higher-level semantic notations. Example higher-level semantic notations are statechart notation and data-flow notation. A test generator processes the hybrid diagram without reducing the higher-level semantic constructs to lower-level semantic constructs. The test generator generates test-generation templates as needed based on the higher-level semantic model used in the diagram. The test generator uses the test-generation templates to generate tests for a system-performing device specified by the diagram. The generated tests may be executed automatically by a test driver or manually by a human tester.

Method and apparatus for test generation from hybrid diagrams with combined data flow and statechart notation

A method for detecting, analyzing, and mitigating vulnerabilities in software is provided. The method includes determining whether one or more vulnerabilities are present in one or more target software components, determining whether any detected vulnerabilities are fixable, and fixing the detected vulnerabilities that are fixable in code or in associated models used to generate code. A vulnerability-covering code is generated when one or more of the detected vulnerabilities are not fixable. A determination is then made whether there are any remaining vulnerabilities in the vulnerability-covering code. A vulnerability-aware diverse code is generated when there are one or more remaining vulnerabilities to obfuscate the remaining vulnerabilities.

Method for software vulnerability flow analysis, generation of vulnerability-covering code, and multi-generation of functionally-equivalent code

An apparatus and methods for generating a plurality of output test vectors from a statechart are provided. The statechart may specify requirements of a system function to be executed by a system-performing device. The statechart comprises a plurality of states, a plurality of transitions, and a plurality of variables. A forward-propagation pass through the statechart may be performed to generate a plurality of forward-reached-transition environments. A backward-propagation pass through the statechart may be performed to generate a plurality of backward-reached-transition environments. The plurality of output test vectors is generated from the plurality of forward-reached-transition environments and/or the plurality of backward-reached-transition environments. A test driver may execute a plurality of tests on the system-performing device, wherein the plurality of tests are based on the plurality of output test vectors.

Method, apparatus, and system for automatic test generation from statecharts

A distributed engine control system is provided. The engine control system includes first and second engine data concentrators. Each of the first and second engine data concentrators include a processor module, a signal conditioning module coupled to the processor module, a data transfer module coupled to the processor module, and a data bus coupled between the first and second engine data concentrators and a hydro-mechanical unit (HMU).

Distributed engine control system

This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functionality and characteristics of a block type, and each block type has associated templates. These templates provide maps for the creation of test values that verify the functionality of particular instances of that block type. Signal propagation allows the generation of diagram-level test cases that verify particular characteristics of a single embedded block. The methods disclosed for signal propagation utilize range intersection, equivalence classes, and block type formulae to create efficient and complete test cases. This test generation method would preferably be repeated until all blocks in a data flow block diagram were verified in their respective contexts, and it creates test cases that cover multiple time steps.

Requirements-based test generation

A framework is provided for generating code for the model-based development of a system. According to the framework, the model-based system is modeled using graphical modeling entities. A modular code generator routine is attached directly to at least one of the graphical modeling entities or to a meta-entity or to a collection of entities. The graphical modeling entities are traversed in order to access specified code generator routines. Each of the accessed code generator routines is executed so as to build up code portion by portion for the system.

Model-based composable code generation

A method for visualizing time-varying data from one or more data streams at a different interval than the interval between acquisition of the individual data items in the data stream. Data received is combined, or aggregated, between updates of a display to retain some information from each element. The aggregated data is then displayed at the next update of the display in a number of display elements. The characteristics of the display elements, and the organization of the elements represent changes in the data streams.

Display of visual data utilizing data aggregation

A circuit for monitoring digital electrical signals which counts events, compares the event count to a threshold value, generates an equal value signal when the threshold is attained and indicates the time elapsed between an initial value and the generation of the equal value signal. The event counter is automatically cleared or reset upon a user enabled automatic clear logic enabling signal. The circuit is preferably configured as a chip employing GaAs Schottky diode field effect transistor logic (SDFL) gates.

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Maple Grove, MN, United States of America

Devesh Bhatt