Intel Corporation

Devendra Natekar

Yoshihiro Tomita

Gregory Martin Chrysler

David Chau

Leonel R Arana

Sriram Muthukumar

Terry Lee Sterrett

Michael W Newman

Charan K Gurumurthy

Chi-won Hwang

An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.

Flexible interconnect pattern on semiconductor package

In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposerincludes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.

Etched interposer for integrated circuit devices

Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

Thin silicon based substrate

A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material property than the matrix, forming a dispersed phase, the resulting composite material having a different material property than the matrix.

Integrated circuit die containing particle-filled through-silicon metal vias with reduced thermal expansion

Horizontal carbon nanotubes may be used for on-die routing and other applications. In one example, a catalyst is applied to a plurality of different points on a substrate. Carbon nanotubes are then grown vertically on the plurality of different points to form a plurality of vertical carbon nanotube structures on the substrate. The vertical carbon nanotuhe structures are then rolled to form horizontal carbon nanotube structures.

Horizontal Carbon Nanotubes by Vertical Growth and Rolling

A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.

Method of forming through-silicon vias with stress buffer collars and resulting devices

Electronic device support and processing methods are described. One embodiment includes a method of processing an electronic device including solder bumps extending therefrom. The method includes providing at least one fluid selected from the group consisting of electrorheological fluids and magnorheological fluids on a support structure. The solder bumps extending from the electronic device are positioned in the fluid. The fluid is activated by applying a field selected from the group consisting of an electric field and a magnetic field to the fluid. The activated fluid mechanically holds the electronic device in place. A surface of the electronic device is polished while the electronic device is held in place by the activated fluid. The fluid is deactivated by removing the applied field from the fluid, and the electronic device is separated from the deactivated fluid. Other embodiments are described and claimed.

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Chandler, AZ, United States of America

Devendra Natekar