Xambala Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Vitesse Semiconductor Corporation

Devendra Kumar Tripathi

Mohan V Kalkunte

Alak Deb

Linh Tien Truong

Namakkal S Sambamurthy

Praveen D Kumar

Debashis Chatterjee

Keith Kong

Sarin Chandran

Raman Muthukrishnan

A route update system (RUS) may support increased efficiency and speed for performing a routing table update. The RUS may include a control plane processor device, which may implement update snoop module circuitry. The RUS may also include a data routing switch, which may implement update inject module circuitry. The RUS may include one or more RUS connectivity systems that link the update snoop module circuitry and the update inject module circuitry.

System for accelerated network route update through exclusive access to routing tables

A structural matching engine for non-deterministic filtering operations is provided. The structural matching engine includes an active node processor (ANP) configured to process a state of an active list to determine possible future states of a non-deterministic finite automaton (NFA). The ANP processes the state according to rules. The structural matching engine includes an active list processor (ALP) configured to initiate a lookup for a token value corresponding to the state of the active list. The ALP provides a next sate of the active list to the ANP for processing according to the rules upon completion of the processing of the state by the ANP, wherein the possible future states of the NFA are linked by the ALP to form a target list, the target list stacked on top of the active list in a data structure. A processor and a method for filtering data associated with non-deterministic states are also included.

Method and system for non-deterministic finite automaton filtering

A system including a CPU including logic for executing code from a location and at a time determined by an external entity, a data cache and a CPU management entity (CME) including logic for receiving data one unit at a time from an external data feeder. The data unit being arbitrarily defined mutually between the data feeder and the CME. The CME being coupled to the CPU. The CME including logic to provide the received data unit, a corresponding context information and a corresponding code address to the CPU, wherein the CPU includes logic for notifying the CME of a completed execution.

Semantic processor systems and methods

Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a lower layer. A receive media access controller that is configured to process in-coming packet data received from the lower layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.

Media access control architectures and network management systems

Growing community of inventors

Union City, CA, United States of America

Devendra Kumar Tripathi