International Business Machines Corporation

Globalfoundries Inc.

King Abdulaziz City for Science and Technology

Bay Zu Precision Co., Ltd

Matheson Tri-gas, Inc.

Egypt Nanotechnology Center

Washington University

Hefechip Corporation Limited

Massachusetts Institute of Technology

The United States of America As Represented by the United States

Toshiba America Electronic Components, Inc.

Elpis Technologies Inc.

The United States of America As Represented by the Department of Commerce

Armonk Business Machines Corporation

Posi Energy&#x2014;silicon Power, LLC

Devendra K Sadana

Stephen W Bedell

Ning Li

Keith E Fogel

Ghavam G Shahidi

Jeehwan Kim

Joel Pereira De Souza

Davood Shahrjerdi

Bahman Hekmatshoartabari

Cheng-Wei Cheng

Kuen-Ting Shiu

Effendi Leobandung

Alexander Reznicek

Katherine Lynn Saenger

Teodor Krassimirov Todorov

Tze-Chiang Chen

Steven J Holmes

Paul Alfred Lauro

Ali Afzali-Ardakani

Kangguo Cheng

Bruce Bennett Doris

Ali Khakifirooz

Tak H Ning

Dominic Joseph Schepis

Hariklia Deligianni

Frank Robert Libsch

Joshua T Smith

Thomas N Adam

Russell Alan Budd

Bing Dang

Meikei Ieong

Juntao Li

Ramachandra Divakaruni

Shu-Jen Han

Jack Oon Chu

Christos Dimitrios Dimitrakopoulos

Guy M Cohen

Dechao Guo

Jae-Woong Nah

Amlan Majumdar

Kevin K Chan

Edmund Juris Sprogis

Wilfried Haensch

Dirk Pfeiffer

Damon B Farmer

Naigang Wang

Jack Allan Mandelman

Vijay Narayanan

Hemanth Jagannathan

George Stojan Tulevski

Edward J Nowak

Chung H Lam

Nicolas J Loubet

Oleg Gluschenkov

Judson Robert Holt

Hong He

Daniel Joseph Friedman

Arvind Kumar

Martin Michael Frank

Shreesh Narasimha

Babar Ali Khan

Ramachandran Muralidhar

Eduard Albert Cartier

Robert H Dennard

Tymon Barwicz

Oki Gunawan

Seyoung Kim

Junli Wang

Carl John Radens

Chen Zhang

Shogo Mochizuki

Haining S Yang

Dureseti Chidambarrao

Mark Charles Hakey

John H Zhang

Ruqiang Bao

Christian Lavoie

Paul Stephen Andry

Bucknell Chapman Webb

Zhen Zhang

Lubomyr Taras Romankiw

Brian Joseph Greene

Huiming Bu

Jason Scott Orcutt

Xiao Hu Liu

Jin Cai

James R Kozloski

Qizhi Liu

Theodore Gerard Van Kessel

Haizhou Yin

Kern Rim

Robert Russell Robison

Alvin Jose Joseph

Michael Patrick Chudzik

Paul Michael Solomon

Roy Rongqing Yu

Robert David Allen

John Michael Cotte

Renee Tong Mo

Ahmet Serkan Ozcan

One or more trenches in a silicon substrate have an electrically active surface at a trench base and metal layer disposed on the electrically active surface. Precursor materials are disposed and/or formed on the metal layer in the trench. An anode is patterned either exclusively in the 3D trench or in the 3D trench, sidewalls and field of the substrate, where the anode patterning transforms and/or moves the precursor materials in the trench into some novel compositions of matter and other final operational structures for the device, e.g. layers of metallic Lithium for energy storage and different concentrations of Lithium-silicon species in the substrate. A multi-faceted mechanism is disclosed for Al2O3 silicon interfacial additives. When the anode is patterned both in and outside the 3D wells, Al2O3 provides an for electron-conductive Li-metal interface that enables homogenous plating on both the insulated substrate field as well as active silicon trench base where Al2O3 acts as a barrier to Li—Si diffusion. When the anode is patterned only in the 3D trench, Al2O3 additive creates a robust, flexible, Li-permeable interface upon charge cycling, which preserves the 3D textured structure of the porous silicon anode. Additionally, the Al2O3 additive is mobilized deeper into the bulk silicon in parallel with Li+ and a conductive plasticizer upon progressive cycling—where the lithiated Al2O3 particles nucleate at defect sites and prevent mechanical degradation of the silicon anode through a combined bridge and spacer mechanism. By selecting different defined anode patterns to deposit on the 3D substrate, final operational characteristics, properties, structures, and charge storage performance for the device can be predictably designed and manufactured.

Aluminum oxide protected lithium metal tunable 3D silicon batteries

Energy storage method using aluminum oxide protected lithium metal tunable 3D silicon batteries

A vertical Josephson Junction (JJ) qubit device that is fabricated from crystalline silicon material is provided. The JJ device has a substrate of epitaxial silicon, a lower superconducting electrode that is a superconducting region of the epitaxial silicon and an upper superconducting electrode of a metallic superconductor. The JJ device also has a junction layer. A section of the junction layer between the lower and upper superconducting electrodes forms a junction of the JJ device. Resonator and/or capacitor wiring of the JJ device is also fabricated using the metallic superconductor. The superconducting region is epitaxial silicon that is doped or implanted with boron or gallium. The substrate, the junction layer, and the implanted epitaxial silicon share a contiguous crystalline structure.

Vertical silicon Josephson Junction device for qubit applications

A bottom electrode, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the bottom electrode, and a top electrode vertically aligned. A phase change material layer, a top electrode adjacent to a first vertical side surface of the phase change material layer, and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. Forming a phase change material layer, forming a top electrode adjacent to a first vertical side surface and overlapping a first portion of an upper horizontal surface of the phase change material layer, forming a bottom electrode, adjacent to a second vertical side surface and overlapping a second portion of the upper horizontal surface of the phase change material layer, and forming a dielectric material horizontally isolating the bottom electrode and the top electrode.

Crossbar memory array in back end of line

Methods for minimizing or eliminating cracks in the crystalline porous-Si structure that can occur during the layer release process and/or during subsequent processing in a lithium-ion battery during charge and discharge cycles. The methods include: modifying the anodic etching process so that a freestanding film of Si with the anode structure is detached from a p-doped substrate; depositing a conductive layer on the back surface of the released porous-Si structure with or without a metallic seed layer; mechanically or chemically thinning the back surface of the Si substrate after forming the porous-Si at the front surface of a thick Si substrate; forming a thin crystalline porous-Si anode structure on a p-doped silicon epitaxy grown on porous-Si with a porous-Si release layer.

Lithium-ion battery with thin crystalline anode and methods of making same

A crystallization seed layer in a substrate, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the crystallization seed layer, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A plurality of memory structures configured in a crossbar array, each including a crystallization seed layer, a phase change material layer above, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A method including forming a crystallization seed layer, forming a phase change material layer, forming a top electrode and a bottom electrode on the substrate, each adjacent to a vertical side surface of the phase change material layer.

Crossbar memory array in back end of line with crystallization front

A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A capacitor having an inner electrode and a node dielectric layer is formed in the substrate. The inner electrode and the node dielectric layer extend into the doped silicon substrate. A select transistor is disposed in the silicon device layer. An embedded contact is disposed atop the capacitor to electrically couple a doped region of the select transistor with the inner electrode. A first dielectric layer is disposed around the select transistor. A second dielectric layer is deposited on the first dielectric layer. A contact plug is formed in the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack with a MTJ element is disposed on the contact plug.

Semiconductor structure and fabrication method thereof

A method for forming a pumped laser structure includes forming a III-V buffer layer on a substrate including one of Si or Ge; forming a light emitting diode (LED) on the buffer layer configured to produce a threshold pump power; forming a photonic crystal layer on the LED and depositing a monolayer semiconductor nanocavity laser on the photonic crystal layer for receiving light through the photonic crystal layer from the LED with an optical pump power greater than the threshold pump power, wherein the LED and the laser are formed monolithically and the LED functions as an optical pump for the laser.

Nanocavity monolayer laser monolithically integrated with LED pump

A computing device is provided. The computing device includes a sapphire substrate having a first surface and a second surface opposed to the first surface, a light receiving device having a first surface and a second surface opposed to the first surface, the second surface of the light receiving device coupled to the first surface of the sapphire substrate, a memory coupled to the first surface of the light receiving device, and an antenna coupled to the first surface of the sapphire substrate.

Silicon on sapphire substrate for edge computer

A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.

Cluster tool for production-worthy fabrication of Dolan bridge quantum Josephson junction devices

A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.

Phase change memory having gradual reset

Making a rechargeable Lithium energy storage device begins by forming one or more trenches in a solid silicon substrate. One or more region interface precursors are deposited in the trench followed by one or more anode materials, one or more solid polymer electrolytes (SPE), and one or more cathode materials. Electrically cycling transforms the battery structures prior to full operation of the battery. Some, or all, of the process steps can be performed while the materials are within the trench, i.e. in-situ.

Method of making a lithium energy storage device

A semiconductor device fabrication method is provided. The semiconductor device fabrication method includes frontside semiconductor device processing on a frontside of a wafer, flipping the wafer, backside semiconductor device processing on a backside of the wafer and backside and frontside contact formation processing on the backside and frontside of the wafer, respectively.

Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer

Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Device integration using carrier wafer

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

Epitaxial Josephson junction device

Growing community of inventors

Pleasantville, NY, United States of America

Devendra K Sadana