Cadence Design Systems, Inc.

Invarium, Inc.

Devendra Joshi

Abdurrahman Sezginer

Chi-Song Horng

Franz X Zach

Bayram Yenikaya

Jesus Orsely Carrero

Anwei Liu

Paul A Fornari

An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at feast one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

Defect filtering optical verification process

A photomask dataset corresponding to a target-pattern is verified by simulating a resist-pattern that will be formed in a resist layer by a lithography process, simulating an etched-pattern that will be etched in a layer by a plasma process wherein said simulation comprises calculating a flux of particles impacting a feature, and determining whether the etched-pattern substantially conforms to the target-pattern.

Method of verifying photomask data based on models of etch and lithography processes

An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at least one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

Defect filtering optical lithography verification process

A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design

A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the other instances of the repeating cluster based on their positions in the exposure field. Or, optical proximity corrections can be applied to the repeating cluster of objects for different values of flare intensity, or another parameter of patterning imperfection, such as by calculating the value of the flare at the location of each instance of the repeating cluster, and interpolating the optical proximity corrections to those values of flare.

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San Jose, CA, United States of America

Devendra Joshi