Qualcomm Incorporated

Devavrata Vasant Godbole

Raghu Narayan Challa

Chiewcharn Narathong

Eugene Robert Worley

Lai Kan Leung

Li Liu

Jeremy Mark Goldblatt

Prasad Srinivasa Siva Gudem

Himanshu Khatri

Soon-Seng Lau

Ketan Humnabadkar

Praveen-Kumar Sampath

Hsuanyu Pan

An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.

Radio frequency integrated circuit (RFIC) charged-device model (CDM) protection

Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.

Phase detection and correction for non-continuous local oscillator generator

A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.

Dynamic divider having interlocking circuit

An exemplary apparatus is disclosed that comprises a plurality of voltage to current transducers to convert an input signal voltage into a plurality of input signal currents and a cascode stage. The cascode stage is coupled to the voltage to current transducers to provide amplifier gain control. The cascode stage comprises a thin gate oxide transistor and a thick gate oxide transistor.

Gain control linearity in an RF driver amplifier transmitter

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Carlsbad, CA, United States of America

Devavrata Vasant Godbole