Intel Corporation

Devan Burke

Travis T Schluessler

Abhishek R Appu

Altug Koker

Subramaniam M Maiyuran

Joydeep Ray

Elmoustapha Ould-Ahmed-Vall

John H Feit

Prasoonkumar Surti

Philip R Laws

Balaji Vembu

Kamal Sinha

Peter L Doyle

Karthik Vaidyanathan

Abhishek Venkatesh

Adam T Lake

Jeffery S Boles

Eriko Nurvitadhi

John G Gierach

Narayan Srinivasa

Justin E Gottschlich

Feng Chen

Linda L Hurd

Sara S Baghsorkhi

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Rajkishore Barik

Dukhwan Kim

Nadathur Rajagopalan Satish

Tsung-Han Lin

Wenyin Fu

Josh B Mastronarde

Farshad Akhbari

Nikos Kaburlasos

Tomer Bar-On

Jacek Kwiatkowski

Sanjeev S Jahagirdar

Murali Ramadoss

Michael Apodaca

Kiran Chand Veernapu

Jonathan Kennedy

Tomasz Janczak

Louis Feng

Slawomir Grajewski

Eric J Asperheim

Ankur N Shah

Kai Xiao

Gabor Liktor

James M Holland

Daniel Pohl

Chandrasekaran Sakthivel

Pattabhiraman K

Andrew T Lauritzen

David M Cimini

Eric J Hoekstra

Radhakrishnan Venkataraman

Sayan Lahiri

Vivek Tiwari

Guei-Yuan Lueh

David M Puffer

Supratim Pal

Gang Y Chen

Joy Chandra

Hong Bin Liao

Ananda V Kommaraju

Hugues Labbe

Amit Bleiweiss

Thomas F Raoux

Oguz Hasan Elibol

Anil Thomas

Dhawal Srivastava

Gokce Keskin

Robert B Taylor

Daniel Walsh

Srividya Karumuri

Tomer Bar On

Subramanian Maiyuran

Pruthvi Gowda Thorehosur Appajigowda

Nishant Patel

Huma Abidi

Jaikrishnan Menon

Wojtek Rajski

Jeremy Brennan

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

Graphics with adaptive temporal adjustments

One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value. The resolve can be a stenciled resolve that automatically bypasses execution of a pixel shader for pixels having clear color data.

Leveraging control surface fast clears to optimize 3D operations

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Order independent asynchronous compute and streaming for graphics

An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Control flow mechanism for execution of graphics processor instructions using active channel packing

Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Dynamic brightness and resolution control in virtual environments

Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

Pre-pass surface analysis to achieve adaptive anti-aliasing modes

Growing community of inventors

Portland, OR, United States of America

Devan Burke