Intersil Americas Inc.

International Rectifier Corporation

Dev Alok Girdhar

Michael D Church

Alexander Kalnitsky

Francois Hebert

Timothy Donald Henson

Jeffrey Michael Johnston

David Paul Jones

Ling Ma

Steven Thomas Peake

Thomas Andrew Jochum

Bogdan M Duduman

Vijay Viswanathan

Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.

Body contact layouts for semiconductor structures

One embodiment is directed towards a method. The method includes forming a drift region of a first conductivity type above or in a substrate. The substrate has first and second surfaces. A first insulator is formed over a first portion of the channel, and which has a first thickness. A second insulator is formed over the second portion of the channel, and which has a second thickness that is less than the first thickness. A first gate is formed over the first insulator. A second gate is formed over the second insulator. A body region of a second conductivity type is formed above or in the substrate.

Method and structure for reducing switching power losses

Methods for forming body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a method comprises: forming a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each body contact, adjacent to the gate, has a width extending parallel to the y-axis that is less than the width of the body contact parallel to the y-axis at a distance on an x-axis from the gate.

Method of forming body contact layouts for semiconductor structures

An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Reduced-noise reference voltage platform for a voltage converter device

A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench.

MOSgated power semiconductor device with source field electrode

An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Method of manufacturing junction barrier schottky diode with dual silicides

A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a 'PowerDie') and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Voltage converter and systems including same

A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.

Integrated trench guarded schottky diode compatible with powerdie, structure and method

A junction barrier Schottky diode has N-type well having a surface and first peak impurity concentration; P-type anode region in surface of the well having second peak impurity concentration; N-type cathode contact region in surface of the well and laterally spaced from a first wall of the anode region having third peak impurity concentration; and first N-type region in surface of the well and laterally spaced from second wall of the anode region having fourth impurity concentration. Center of the spaced region between the first N-type region and the second wall of the anode region has fifth peak impurity concentration. Ohmic contact is made to the anode region and cathode contact region. Schottky contact is made to the first N-type region. First and fifth peak impurity concentrations are less than the fourth peak impurity concentration. The fourth peak impurity concentration is less than the second and third peak impurity concentrations.

Junction barrier Schottky diode

An improved organization for a MOSFET pair mounts first and second FET dies in an overlying or stacked relationship to reduce the surface area 'footprint' of the MOSFET pair. The source and drain of a high side FETand a low side FETor the drains of the respective high side FETand low side FETare bonded together, either directly or through an intermediate conductive ribbon or clip, to establish a common source/drain or drain/drain node that functions as the switch or phase node of the device. The stacked organization allows for lower-cost packaging that results in a significant reduction in the surface area footprint of the device and reduces parasitic impedance relative to the prior side-by-side organization and allows for improved heat sinking.

Stacked field effect transistor configurations

A power semiconductor device that includes a trench power MOSFET with deep source field electrodes and an integrated Schottky diode.

Growing community of inventors

Indialantic, FL, United States of America

Dev Alok Girdhar