Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

Dev Alok

Emil Arnold

Satyendranath Mukherjee

Theodore James Letavic

Nikhil R Taskar

Richard H Egloff

Rik Jos

Semiconductor power devices with improved electrical characteristics are disclosed including rectifying contacts on a specially prepared semiconductor surface with little or no additional exposure to other chemical treatments, with oxide passivation and edge termination at a face of the semiconductor substrate adjacent to and surrounding the power device. The edge termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize a portion of the substrate face and preferably self-aligned to the device. The passivated, edge-terminated devices exhibit improved characteristics relative to passivated devices with characteristics approaching those of the native semiconductor with the additional advantages of passivation protection. Methods for making and using the devices are also disclosed.

Passivated silicon carbide devices with low leakage current and method of fabricating

A silicon carbide lateral metal-oxide-semiconductor field-effect transistor (SiC LMOSFET) having a self-aligned drift region and method for forming the same is provided. Specifically, the SiC LMOSFET includes a source region, a drift region and a drain region. The source and drain regions are implanted using non self-aligned technology (i.e., prior to formation of the gate electrode and the gate oxide layer), while the drift region is implanted using self-aligned technology (i.e., after formation of the gate electrode and the gate oxide layer). By self-aligning the drift region to the gate electrode, the overlap between the two is minimized, which reduces the capacitance of the device. When capacitance is reduced, performance is improved.

Silicon carbide lateral metal-oxide semiconductor field-effect transistor having a self-aligned drift region and method for forming the same

A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) includes a layer of silicon carbide semiconductor material having a p-type conductivity, source and drain regions having n-type conductivities disposed in the silicon carbide semiconductor layer, and an insulated gate electrode disposed on the silicon carbide semiconductor layer. A silicon carbide semiconductor substrate having an n-type conductivity, supports the silicon carbide semiconductor layer. A second layer of silicon carbide semiconductor material having a p-type conductivity, is disposed between the substrate and the first silicon carbide semiconductor layer to prevent parasitic transistor effects. A sinker region having an n-type conductivity extends from the source contact to the silicon carbide semiconductor substrate to ground the substrate.

Silicon carbide n-channel power LMOSFET

A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

Method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor

Superior silicon carbide integrated circuits and method of fabricating

Method achieving higher inversion layer mobility in novel silicon carbide semiconductor devices

A silicon carbide LMOSFET having a self-aligned gate with gate reach-through protection and method for making same. The LMOSFET includes a first layer of SiC semiconductor material having a p-type conductivity and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. An etched trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material thereby forming a gate structure. A channel region is defined in the first layer beneath the gate structure. The gate structure is rounded or buried to provide a current path in the channel region which avoids sharp corners.

Silicon carbide LMOSFET with gate reach-through protection

A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, includes a first layer of SiC semiconductor material having a p-type conductivity, and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. The n-type conductivities of the source and drain regions are greater than the n-type conductivity of the second SiC layer. A trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material. The layers of oxide and metallic material form a gate structure. A channel region is defined in the first layer beneath the gate structure, and electrical contacts associated with the source and drain regions, and the gate structure, establish source, drain, and gate electrodes of the LMOSFET.

Self-aligned silicon carbide LMOSFET

The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices. Such devices are derived from a method for forming a silicon region on a silicon carbide substrate which comprises the steps of: providing a monocrystalline silicon carbide substrate; amorphizing at least one region of the substrate, preferably by subjecting at least a portion of a surface of the substrate to ion implantation to convert at least a portion of the substrate surface to amorphous silicon carbide producing a region of amorphous silicon carbide on a monocrystalline silicon carbide substrate; removing at least an effective amount of carbon from said amorphized region, preferably by subjecting at least a portion of the amorphous silicon carbide region to an etchant material which selectively removes carbon to produce a region of amorphous silicon on a monocrystalline silicon carbide substrate; and subjecting the monocrystalline substrate with at least a region of amorphous silicon to high temperature thermal anneal to produce a region of monocrystalline silicon on said monocrystalline silicon carbide substrate.

A method of forming a laterally-varying charge profile in a silicon carbide substrate includes the steps of forming a silicon nitride layer on a polysilicon layer formed on the silicon carbide substrate, and patterning the silicon nitride layer to provide a plurality of silicon nitrite layer segments which are spaced apart in the lateral direction and which are provided with openings therebetween which are of varying widths. The polysilicon layer is oxidized using the layer segments as an oxidation mask to form a silicon dioxide layer of varying thickness from the polysilicon layer and to form a polysilicon layer portion therebeneath of varying thickness. The silicon dioxide layer and silicon nitride layer segments are removed, and a dopant is ion implanted into the silicon carbide substrate using the polysilicon layer portion of varying thickness as an implantation mask to form a laterally-varying charge profile in the silicon carbide substrate. This method provides an effective and commercially-feasible technique for forming various high-power lateral semiconductor devices, including MOSFET, JFET, diode and IGBT structures, with excellent high-temperature and high-power operating characteristics.

Method of forming a laterally-varying charge profile in silicon carbide

A lateral silicon carbide (SiC) semiconductor device includes a SIC substrate of a first conductivity type, a SiC epitaxial layer of the first conductivity type on the substrate and a SiC surface layer on the SiC epitaxial layer. The SiC surface layer has a SiC first region of the first conductivity type, a SiC lateral drift region of a second conductivity type opposite to that of the first conductivity type adjacent the first region and forming a p-n junction therewith, and a SiC second region of the second conductivity type spaced apart from the first region by the drift region. By providing the drift region with a variable doping level which increases in a direction from the first region to the second region, compact SiC semiconductor devices such as high-voltage diodes or MOSFETs can be formed which can operate at high voltages, high temperatures and high frequencies, thus providing a substantial advantage over known devices.

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Danbury, CT, United States of America

Dev Alok