Qimonda Ag

Infineon Technologies Ag

Qimonda Flash Gmbh

Siemens Aktiengesellschaft

Qimonda Flash Gmbh & Co. Kg

Infineon Technologies Flash Gmbh & Co. Kg

Detlev Richter

Andreas Kux

Wolfgang Anton Spirkl

Gert Koebernik

Josef Willer

Konrad Seidel

Luca De Ambroggi

Andreas Taeuber

Michael Scheppler

Jan Gutsche

Girolamo Gallo

Doris Keitel-Schulz

Roderick McConnell

Christoph Friederich

Roberto Ravasio

Ramirez Xavier Veredas

Helmut Schwalm

Xavier Veredas-Ramirez

Roderick Mc Connell

Mirko Reissmann

Rainer Spielberg

Franz Hofmann

Nicolas Nagel

Michael Specht

Dirk Manger

Klaus Knobloch

Sebastian Kuhne

Robert Petter

Steffen Meyer

Uwe Augustin

Thomas Janik

Gert Koebernick

Volker Zipprich-Rasch

Jens Braun

Eike Ruttkowski

Juergen Engelhardt

Sudhindra Prasad

Gert Köbernik

Hans Heitzer

Daniel-André Löhr

Sören Irmer

Roland Weigand

Marco Ziegelmayer

Joseph Willer

Kenny Oisin

Holger Moeller

Doris Keitel Schulz

A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Memory read-out

In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Memory device and method providing logic connections for data transfer

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.

Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a memory cell block having a plurality of memory cells, a storage portion configured to store information about a quality characteristic of the memory cells of the memory cell block, and a controller configured to control a read operation, and to change the information about the quality characteristic depending on a quality of a read operation.

Integrated circuits having a controller to control a read operation and methods for operating the same

A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.

Method for classifying memory cells in an integrated circuit

Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.

Integrated circuit and method to operate an integrated circuit

Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.

Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings

In one embodiment of the invention, a method of operating a memory system is provided, including concurrently reading data from a plurality of memories of the memory system and outputting the data from the memory system at an output channel capacity of an I/O port of the memory system by converting a data bus width of data read from at least some of the plurality of memories to a data bus width of the I/O port.

Data bus width converter

Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

Integrated circuit having NAND memory cell strings

A method of storing data in a memory is provided, including testing a plurality of memory cells of a plurality of memory cell sectors. Each memory cell sector includes a plurality of memory cells. Each memory cell sector is classified into at least one quality class of a plurality of quality classes depending on the results of the testing of the memory cells of the respective memory cell sector. Data is stored in the memory cells of the classified memory cell sectors depending on the quality class of the respective memory cell sector.

Memories, method of storing data in memory and method of determining memory cell sector quality

Embodiments of the invention relate generally to a method for writing at least one memory cell of an integrated circuit; a method for writing at least two memory cells of an integrated circuit; and to integrated circuits. In an embodiment of the invention, a method for writing at least one memory cell of an integrated circuit is provided. The method includes determining a writing state of at least one reference memory cell, depending on the writing state of the at least one reference memory cell, writing the at least one memory cell, and writing the at least one reference memory cell to a given writing state.

Method of operating an integrated circuit having at least one memory cell

Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems

In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level.

Integrated circuits, memory controller, and memory modules

In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.

Method of operating an integrated circuit for reading the logical state of a memory cell

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Munich, Germany

Detlev Richter