National Semiconductor Corporation

Silicon Graphics, Incorporated

Desmond W Young

James R Hamstra

Mark A Travaglio

Kianoosh Naghshineh

Ramanatha V Balakrishnan

David C Brief

Daniel Yau

Jeannine Marie Smith

Greg Chesson

Yuh-wen Lin

In-whan Choi

William D Schwaderer

An interface system for transferring information between a local area network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system. An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Automatic preemption recovery and frame repeat option in a media access

I/O data unit symmetry in a media access control/host system interface

An interface system for transferring information between a local area-network and a system memory associated with a station attached to the network. The interface system includes a bus interface unit for implementing the transfer of information between the interface system and the memory system, An indicate module transfers information received by the interface system from the network to the memory system via the bus interface unit. A request module transfers information received by the interface system from the memory system via the bus interface unit to the network. A status generation/space management module connected to the indicate module and to the request module monitors the status thereof and generates corresponding status signals and manages the allocation of storage space in the memory system for information transferred between the network and the memory system via the interface system.

Status batching and filtering in a media access control/host system

A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Central processing unit for processing a plurality of threads using

Transmit data descriptor structure in a media access control/host system

Method and apparatus for receive frame sorting in a media access

Method and apparatus for frame header splitting in a media access

A high performance shared-bus signal detection mechanism comprises a plurality of access event registers, an address comparator, an event masking component, and a local processor access detector. The comparator component couples to a bus providing access to a shared memory address space. The bus can be used by a single processor or shared by a plurality of processors. A processor loads the address event registers with address base and extent values and type of access notification desired. As addresses and access-type signals appear on the bus, the comparator simultaneously compares the bus information to access event register information to determine if the bus access meets access event register criteria. When matches occur, the comparator emits an appropriate signal to an event masking component. The local processor also loads the event masking component to selectively mask off unwanted event notifications as well as those performed by itself. The event masking component emits signals which feed a general-purpose or special-purpose processors such as interrupt controllers.

Apparatus and method for detecting the activities of a plurality of

A system for reducing skew in the parallel transmission of digital data slices is provided. The system includes a transmitter unit comprising a plurality of transmitter memory devices. Control logic provides a strobe signal to each transmitter unit memory device to implement the transfer of a desired number of data characters from the transmitter unit to a receiver unit. Both its associated data slice and the strobe signal are transferred from each transmitter unit memory device to the bus via an associated transmitter unit bus driver. Each data slice and its associated strobe signal are then transferred from the bus to a corresponding receiver unit memory device via a corresponding receiver unit bus receiver device. Each receiver unit memory device includes means for generating a 'receiver-full' status signal that indicates that all data slices transferred from the corresponding transmitter unit memory device have been received. These 'receiver-full' status signals are monitored and a 'transfer-done' status signal is issued when all data slices transferred from the transmitter unit have been received by the receiver unit. Skew within a particular transmission path is compensated for by providing a controlled delay path for the clock signal in each device within that path.

System for reducing skew in the parallel transmission of multi-bit data

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Campbell, CA, United States of America

Desmond W Young