Texas Instruments Corporation

Desmond Pravin Martin Fernandes

Indu Prathapan

Sundarrajan Rangachari

Saket Jalan

Rakesh Channabasappa Yaraduyathinahalli

Prashanth Saraf

In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

Error-correcting code memory

Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.

Memory compression operable for non-contiguous write/read addresses

Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.

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Bengaluru, India

Desmond Pravin Martin Fernandes