Altera Corporation

Ross Video Limited

Desmond Leslie Ambrose

Kent Orthner

Geoff Barnes

Andrew Martyn Draper

Christopher Jason Williams

Scott Raymond Kaneta

Glenn Henshaw

Antoine Alary

In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.

Data alignment implemented in a field programmable gate array (FPGA) device

Methods and apparatus are provided for allowing components such as buffers, multiplexers, ingress cores, etc. on a device such as a programmable chip to configure themselves based on parameter information. In some examples, self-configuring components obtain parameter information from adjacent components. In other examples, self-configuring components obtain parameter information from a system environment or a processor register. Component self-configuration can occur at a variety of times including preprocessing, simulation, and run-time.

Self-configuring components on a device

Techniques for processing overhead bytes in SONET or SDH frames are provided. Memory stores overhead bytes from the SONET (or SDH) frames. One or more processors load the overhead bytes from the memory. The one or more processors can process the overhead bytes away from the data path at a slower data rate than the data rate of data on the data path. By processing the overhead bytes at a slower data rate, less circuitry is needed to process the overhead bytes. Bytes on the data path are stored in a first-in-first-out delay buffer, while the overhead bytes are processed away from the data path, to maintain alignment between output signals of the processors and bytes on the data path.

Efficient delayed overhead processing techniques

Methods and apparatus are provided for allowing flexible on-chip datapath interfaces on a device. Datapath connections allow data streamlining without any knowledge of channels or packet boundaries. Flexible and modular interface adapters are used to allow component designers to efficiently provide interoperable components without having to adhere to a strict datapath interface specification. Interface adapters from an adapter library are instantiated and configured automatically when two components are connected.

Flexible on-chip datapath interface having first and second component interfaces wherein communication is determined based on a type of credit condition

Flexible on-chip datapath interface for facilitating communication between first and second interfaces with different interface properties

A system receives input data frames that are configured according to a SONET or an SDH standard. The input data is converted to parallel data. The system provides groups of bits along parallel signal lines. In each group of bits, N contiguous bits in the group form a complete word of input data. The system identifies the boundary between complete words in the input data by comparing subsets of the bits to predefined framing patterns. The system then aligns the input data based on the location of each word using the boundary information. The output data of the system includes data that is word aligned. The system can also detect boundaries between the frames.

Techniques for frame detection and word alignment

Techniques for aligning the data path inside a receiver to the word and frame boundaries of an input data stream using reconfigurable programmable circuit elements are provided. The input data stream can be organized according to a data transmission protocol such as SONET or SDH. A first programmable circuit elements are initially configured as a frame detection block. The frame detection block detects the boundaries between words in the input data. A portion of the frame detection block is then reconfigured as a word align block. Another portion of the frame detection block is reconfigured as a block that monitors bits in each frame to ensure that the frame boundaries remain in the same bit positions. If the frame boundaries change, the programmable circuit elements are reconfigured to implement the frame detection block again.

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Ottawa, Canada

Desmond Leslie Ambrose