Altera Corporation

Amazon Technologies, Inc.

Deshanand Pratap Singh

Stephen D Brown

Valavan Manohararajah

Gordon Raymond Chiu

Terry Borer

Doris Tzu Lang Chen

Gabriel Quan

Ivan Blunno

Chris Sanford

Karl Schabas

Doris Tzu-Lang Chen

Vaughn Betz

Jordan Swartz

John Stuart Freeman

Ivan Hamer

Caroline Pantofaru

Kevin Chan

Ian Chesal

Paul McHardy

Andrew Hall

Shawn Malhotra

Peter Yiannacouras

Doris Chen

Joshua David Fender

David Neto

Tomasz Czajkowski

Andrew Ling

Tim Michael Vanderhoek

Dmitry Nikolai Denisenko

Clement Tse

Przemek Guzy

Steven Caranci

Alexander Grbic

Carolyn Lam-Leventis

Jimmy Kuo

Rebecca Katzin

Zvonko Vranesic

Jason Wong

Tian Yi David Han

Systems and methods to warehouse, handle, and deliver products are disclosed. The system can comprise a vendor-based virtual network that is associated with a supplier-based physical network. The system can enable vendors with institutional, market, or industry knowledge to manage inventory, logistics, and delivery more efficiently. The system can enable vendors to configure a virtual warehouse and delivery network based on the institutional, market, or industry knowledge. The virtual network can be mapped&#x2014;behind the scenes&#x2014;to physical warehouses and delivery networks by warehousing providers ('providers') based at least in part on the virtual network. The provider can then adjust the physical network based on market knowledge, research, physical sales, warehouse and personnel availability, weather, and other factors. The provider can also offer periodic data to the vendor based on physical sales and delivery information to enable both the virtual and physical networks to converge on an efficient solution.

Virtual logistical network overlay for physical logistical network

A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

Method and apparatus for implementing configurable streaming networks

A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.

M/A for compiling parallel program having barrier synchronization for programmable hardware

A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. That compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.

Configuring a programmable device using high-level language

A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.

Method apparatus for high-level programs with general control flow

A method for designing a system on a target device includes describing the system in a high-level synthesis language where the system includes a configurable clock to drive the system at a specified clock frequency. A hardware description language (HDL) of the system is generated from the high-level synthesis language. An initial compilation of the HDL of the system is performed in response to the specified clock frequency. Timing analysis is performed on the system after the initial compilation of the HDL to determine a maximum frequency which the system can be driven. The configurable clock is programmed to drive the system at the maximum frequency.

Method and apparatus for satisfying operating conditions in a system design using an electronic design automation tool

A method for designing a system on a target device includes identifying a soft processor to implement on the target device. The soft processor is optimized in response to code to be executed on the soft processor. Other embodiments are also disclosed.

Method and apparatus for optimizing implementation of a soft processor executing a fixed program on a target device

A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.

Guided memory buffer allocation

Method and apparatus for high-level programs with general control flow

A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Method and apparatus for performing multiple stage physical synthesis

A method of configuring an integrated circuit device to perform a function includes storing a plurality of configurations for performing the function, each of the configurations being designed for a different characteristic of a particular input to the function. Inputs are received for the function, including the particular input. The characteristic of the particular input as received is examined, and one of the plurality of configurations is instantiated based on that characteristic of the particular input as received. A machine-readable data storage medium may be encoded with instructions to perform the method. A programmable device may be configured according to the method, and also may be incorporated into a heterogeneous system.

Multiple alternate configurations for an integrated circuit device

Growing community of inventors

Toronto, Canada

Deshanand Pratap Singh