Intel Corporation

Other

Lockheed Martin Corporation

Derwin Jallice

Joseph Andrew Hoffman

Bin Li

Bryan P Black

Edward A Brekelbaum

Jeffrey P Rupley, Ii

Donald W McCauley

Mohammed Hasan Taufique

John P DeVale

Ho Gia Phan

Gabriel H Loh

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Memory array on more than one die

A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Method and apparatus for hardening a static random access memory cell from single event upsets

A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The first and second sets of isolation transistors are coupled to the first and second set of cross-coupled transistors, respectively, such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Single event upset (SEU) hardened static random access memory cell

Growing community of inventors

Austin, TX, United States of America

Derwin Jallice