Xilinx, Inc.

Derrick S Woods

Weiguang Lu

Jason J Moore

David A Knol

Stephen P Rozum

Chen Wei Tseng

W Story Leavesley, Iii

Sudipto Chakraborty

Brendan K Bridgford

William W Stiehl

Carl M Stern

Robert M Balzli, Jr

Aditya Chaubal

Ryan Linderman

A method, non-transitory computer readable medium and apparatus for using an out-of-context sub-block in a hierarchical design flow for an integrated circuit are disclosed. For example, the method identifies one or more sub-blocks in the hierarchical design flow that are eligible for creating the out-of-context sub-block, receives a selection of one of the one or more sub-blocks that are eligible and creates the out-of-context sub-block for the one of the one or more sub-blocks that is selected.

Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows

When a first sub-circuit of a programmable integrated circuit ('IC') is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.

Power control using global control signal to selected circuitry in a programmable integrated circuit

A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.

Verification of logic core implementation

Growing community of inventors

Loveland, CO, United States of America

Derrick S Woods