Cypress Semiconductor Corporation

Camgian Microsystems Corp.

Derrick J Savage

Jeffery Scott Hunt

Muthukumar Nagarajan

David Robert Lindley

Gary Butler

Pidugu L Narayana

Daniel Eric Cress

Andrew L Hawkins

Satish C Saripella

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Multiple sensor data processor interface and relay

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner. Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

A circuit and method comprising a multiplexer circuit, a select circuit and a buffer circuit. The multiplexer circuit may be configured to present a data bit in response to a first control signal. The select circuit may be configured to generate one or more first outputs in response to (i) the data bit and (ii) one or more first select signals. The buffer circuit may be configured to present one or more second outputs on a data bus in response to (i) the one or more first outputs and (ii) one or more second control signals. One of the second outputs may have a data state and the rest of the second outputs may have a high impedance state. The first and select signals may be generated by a logic circuit.

Column redundancy scheme for bus-matching fifos

An apparatus comprising a first circuit, a second circuit and a switch. The first circuit may be configured to receive a first supply voltage and may be coupled to a first ground. The second circuit may be configured to receive a second supply voltage and may be coupled to a second ground. The second circuit may be disabled in response to a control signal. The first and second supply voltages may be controlled by a reference voltage. The switch may be coupled between the first and second circuits and may be configured to connect the first and second circuits when the second circuit is disabled.

Method, circuit and/or architecture for reducing gate oxide stress in low-voltage regulated devices

A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.

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Starkville, MS, United States of America

Derrick J Savage