Western Digital Technologies, Inc.

Derrick E Burton

Weldon Mark Hanson

Richard Leo Galbraith

Iouri Oboukhov

Niranjay Ravindran

Masahito Kobayashi

Satoshi Yamamoto

Robert L Horn

James N Malina

Robert G Biskeborn

Thao Hieu Banh

Tom S Chan

John Thomas Contreras

Bernhard E Knigge

Jonas Andrew Goode

Phillip Scott Haralson

Naoto Ito

Mark L Watson

Pradhan Bellam

Michael J Ross

Michael J Therrien

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

Channel circuit with asynchronous sampling from an oversampled analog-to-digital converter

Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The one or more processing devices are configured to generate a map of laser mode hop effects across the corresponding disk surface, for the selected head. The one or more processing devices are further configured to apply a laser mode hop mitigation in operating the selected head, based on the map of laser mode hop effects.

Data storage device with mapping and mitigation of laser mode hop effects in heat-assisted magnetic recording (HAMR)

Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Adjustable code rates and dynamic ECC in a data storage device

The present disclosure generally relates to a tape drive comprising a tape head and control circuitry. The tape head comprises a plurality of data elements, each data element including a write transducer and a read transducer. The control circuitry is configured to control the tape head to write at least three different frequency preamble tones prior to writing data to data tracks of a tape. A different preamble tone is written to adjacent data tracks of the tape. The data elements of the tape head are each configured to read one or more preamble tones prior to writing data to or reading data from the tape. The control circuitry is then configured to extract a signal content from each preamble tone read by each data element, and determine an optimized positioning for the tape head with respect to the tape to reduce alignment errors.

TDS mitigation using different data preamble tones

Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix based on write verification determining extended parity are described. A data unit with a base set of parity bits may be written to a non-volatile storage medium and then read back for write verification. The data unit may be decoded using the base set of parity bits and corresponding primary parity matrix. Based on the decoding of the write verification read signal, a number of parity bits for an extended set of parity bits may be determined and the extended set of parity bits may be stored to an extended parity storage location for use during subsequent read operations.

Adjustable code rates and dynamic ECC in a data storage device with write verification

Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.

Oversampled phase lock loop in a read channel

Example control circuitry, data storage devices, and methods to provide a spiral data track format that is different from the underlying servo track format are described. The data storage device may include a storage medium configured with a plurality of tracks in at least one continuous spiral pattern and a head actuated over the storage medium. The data tracks may be written to the storage medium with track lengths that are different than a single revolution of the storage medium.

Offset spiral data track format for data storage devices

Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.

Extendable parity code matrix construction and utilization in a data storage device

A Data Storage Device (DSD) includes one or more magnetic disks. One or more data blocks are encoded into a first plurality of Error Correction Code (ECC) sub-blocks including a first ECC sub-block. The first plurality of ECC sub-blocks is encoded into a first ECC super-block. The first ECC sub-block is write-verified by reading the first ECC super-block. If the write-verify passes, a second plurality of ECC sub-blocks is encoded into a subsequent ECC super-block. If the write-verify fails, the first ECC sub-block and a subset of the second plurality of ECC sub-blocks are encoded into the subsequent ECC super-block. In another aspect, in response to the first ECC super-block failing to recover the first ECC sub-block, a subsequent ECC super-block is read and a copy of the first ECC sub-block is used if the copy is detected in the subsequent ECC super-block.

Data error correction for magnetic disks

The present disclosure generally relates to a tape head and a tape drive including a tape head. The tape head comprises servo heads configured to read servo data from a tape, a plurality of write heads configured to: write user data to a plurality of data tracks of the tape and write embedded servo data into one or more data fields of the tape, the embedded servo data comprising servo positioning information, and a plurality of read heads configured to read the user data and the embedded servo data from the tape. The embedded servo data may be embedded servo fields or embedded servo tracks. The embedded servo data allows the tape head to be accurately controlled and positioned above the tape, and for new data to be accurately appended to the tape.

Hybrid dedicated and dynamic servo for tape

A data storage device configured to access a magnetic tape is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A first plurality of data blocks are encoded into a first plurality of ECC sub-blocks including a first ECC sub-block, and the first plurality of ECC sub-blocks are encoded into a first ECC super-block. The first ECC sub-block is written to the magnetic tape, and a write-verify of the first ECC sub-block is executed by reading the first ECC sub-block. When the write-verify passes, a second plurality of data blocks are encoded into a second ECC super-block, and when the write-verify fails, a third plurality of data blocks and the first ECC sub-block are encoded into the second ECC super-block, wherein the second ECC super-block is written to the magnetic tape.

Data storage device duplicating an ECC sub-block in downstream ECC super-block

A data storage device is disclosed comprising at least one head configured to access a magnetic tape comprising a plurality of servo frames each comprising an A servo burst, a B servo burst, a C servo burst, and a D servo burst. The A servo burst in a first servo frame is read using the head to generate a first read signal which is sampled to generate first signal samples. A first matched filter matched to the A servo burst filters the first signal samples to generate first filtered samples within a first burst window, and the first burst window is updated based on the first filtered samples. The first filtered samples within the first burst window are processed to generate a position error signal (PES), and a position of the head is controlled relative to the magnetic tape based on the PES.

Data storage device demodulating servo stripes using matched filter

A data storage device is disclosed comprising at least one head configured to access a magnetic tape comprising a plurality of servo frames each comprising a plurality of servo bursts. A first servo burst is read using the head to generate a read signal which is sampled to generate signal samples. A first matched filter matched to the first servo burst is used to generate filtered samples in response to the signal samples, and at least part of the filtered samples are interpolated to generate interpolated samples. The interpolated samples are processed to generate a position error signal (PES), and a position of the head relative to the magnetic tape is controlled based on the PES.

A data storage device is disclosed comprising at least one head configured to access a magnetic tape comprising a plurality of servo frames each comprising a plurality of servo bursts, wherein each servo burst comprises a plurality of servo stripes. The servo stripes in a first servo burst are read using the head to generate a first read signal that is processed using a first matched filter matched to the first servo burst in order to generate an average time stamp for the servo stripes in the first servo burst. A position error signal (PES) is generated based on the average time stamp of the first servo burst, and the head is positioned relative to the magnetic tape based on the PES.

A data storage device configured to access a magnetic tape is disclosed comprising a plurality of data tracks. A first head is configured to access a first data track comprising a first sync mark, and a second head is configured to access a second data track comprising a second sync mark. The first head is used to read first data from the first data track, wherein the first data comprises a plurality of symbols, and the second head is used to read the second sync mark from the second data track. The first data is symbol synchronized based on the second head reading the second sync mark from the second data track.

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Ladera Ranch, CA, United States of America

Derrick E Burton