International Business Machines Corporation

Infineon Technologies North America Corp.

Derren Neylon Dunn

Michael A Guillorn

Jing Sha

Shawn Peter Fetterolf

Daniel A Corliss

Ekmini Anuja De Silva

Chih-Chao Yang

Lawrence Alfred Clevenger

Timothy Joseph Dalton

Thomas M Shaw

Yun-Yu Wang

James J Demarest

Michael Wayne Lane

Scott Marshall Mansfield

Darryl D Restaino

Ioana C Graur

Philip L Flaitz

Stefanie Ruth Chiras

Martin Burkhardt

Chester T Dziobkowski

James R Lloyd

Michael M Crouse

Soon-Cheon Seo

Stephen Mark Rossnagel

Nelson M Felix

Dongbing Shao

Nicole A Saulnier

Scott David Halle

Henning Haffner

Robin Hsin Kuo Chao

Michael E Scaman

Ravi K Bonam

Kyong Min Yeo

Hyungjun Kim

Predictive multi-stage modelling for complex semiconductor device manufacturing process control is provided. In one aspect, a method of predictive multi-stage modelling for controlling a complex semiconductor device manufacturing process includes: collecting geometrical data from metrology measurements made at select stages of the manufacturing process; and making an outcome probability prediction at each of the select stages using a multiplicative kernel Gaussian process, wherein the outcome probability prediction is a function of a current stage and all prior stages. Machine-learning models can be trained for each of the select stages of the manufacturing process using the multiplicative kernel Gaussian process. The machine-learning models can be used to provide probabilistic predictions for a final outcome in real-time for production wafers. The probabilistic predictions can then be used to select production wafers for rework, sort, scrap or disposition.

Predictive multi-stage modelling for complex process control

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Electrical mask validation

A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

Automatic generation of via patterns with coordinate-based recurrent neural network (RNN)

An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moir&#xe9; pattern.

Semiconductor structure for optical validation

A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.

Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing

Techniques for modifying a mask fabrication process based the identification of an abnormality in a pattern of a fabricated lithography mask are disclosed including comparing a fabricated lithography mask to a lithography mask design where the fabricated lithography mask is fabricated based at least in part on the lithography mask design using a mask fabrication process. An abnormality in a pattern of the fabricated lithography mask relative to a corresponding one of the plurality of patterns in the lithography mask design is identified based at least in part on the comparison of the fabricated lithography mask to the lithography mask design. A calibrated mask model is generated based at least in part on the identified abnormality in the pattern of the fabricated lithography mask and the mask fabrication process is modified based at least in part on the calibrated mask model.

Mask process aware calibration using mask pattern fidelity inspections

A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.

Generative adversarial networks for generating physical design layout patterns of integrated multi-layers

A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Generative adversarial networks for generating physical design layout patterns

A system, a computer program product, and method for physically fabricating an electronic circuit using design space exploration as part of a design process is described. The method begins with defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters. Next an output target to be optimized is defined. A series of one or more test mask shapes are generated to appear on a photo mask using the plurality of design space parameters. A simulation of a post lithography or etch on the series of one or more test mask shapes is performed to produce simulation output values. Next, the simulation output values and corresponding design space parameters are fed into to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate.

Space exploration with Bayesian inference

A method of modeling distributions of post-lithography critical dimensions includes the following steps. A plurality of aerial images of respective portions of a physical design layout of a semiconductor wafer are generated, and the plurality of aerial images are employed as training data. In the method, first and second portions of a neural network architecture are generated. The first portion includes a neural network which is shared by a plurality of output channels, and the second portion includes a plurality of neural networks, wherein each of the plurality of neural networks respectively correspond to one of the plurality of output channels. The method further includes training the first and second portions of the neural network architecture with the training data, and outputting the distributions of the post-lithography critical dimensions based on the plurality of output channels.

Modeling post-lithography stochastic critical dimension variation with multi-task neural networks

A method is presented for generating a plurality of physical design layout patterns. The method includes selecting one or more physical design layouts for neural network training, converting the plurality of physical design layout patterns into coordinate arrays, a coordinate array of the coordinate arrays including via center coordinates of vias in a physical design layout pattern of the plurality of physical design layout patterns, training, by employing the coordinate arrays, a variational autoencoder (VAE), and generating one or more new synthetic coordinate arrays by employing the trained VAE, a synthetic coordinate array of the one or more new synthetic coordinate arrays including via center coordinates of vias for a new physical design layout pattern.

Coordinates-based variational autoencoder for generating synthetic via layout patterns

A method for generating physical design layout patterns includes the step of selecting one or more physical design layouts, a given physical design layout comprising a set of physical design layout patterns for features in at least one layer of a given patterned structure. The method also includes the step of converting the physical design layout patterns into coordinate arrays, a given coordinate array comprising feature center coordinates for the features in a given one of the physical design layout patterns. The method further includes the step of training, utilizing the coordinate arrays, a generative adversarial network (GAN) comprising discriminator and generator neural networks. The method further includes the step of generating one or more synthetic coordinate arrays utilizing the trained generator neural network of the GAN, a given one of the synthetic coordinate arrays comprising feature center coordinates of features for a new physical design layout pattern.

Coordinates-based generative adversarial networks for generating synthetic physical design layout patterns

A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

A computer-implemented method, computer program product, and computer processing system are provided for generating synthetic layout patterns. The method includes receiving, by a processor, a set of physical design layouts that include a variety of layout patterns for neural network training. The method further includes generating, by the processor, a set of training layout pattern images for the neural network training by performing automatic image capturing on the set of physical design layouts with scripts. The method also includes training, by the processor, a feedforward neural network (FFNN)-based Variational Autoencoder (VAE) with the set of training layout pattern images. The method additionally includes generating, by the processor using the FFNN-based VAE, new synthetic layout images.

Growing community of inventors

Sandy Hook, CT, United States of America

Derren Neylon Dunn