Cadence Design Systems, Inc.

Derong Liu

Mehmet Can Yildiz

Zhuo Li

Charles Jay Alpert

Gracieli Posser

Wing-Kai Chow

Yi-Xiao Ding

Wen-Hao Liu

Thomas Andrew Newton

Jhih-Rong Gao

Wing Kai Chow

Aspects of the present disclosure address systems and methods for layer trimming based on resistance and capacitance (RC) values. Data describing an integrated circuit (IC) design is accessed. The IC design comprises a net and a set of routing layers. A first and second list are generated based on the set of layers. The first list comprises horizontal routing layers and the second list comprises vertical routing layers from the set of routing layers. A permitted range of RC values for routing layers in the IC design are determined. The first and second lists are filtered based on the permitted range of RC values. The first and second filtered lists are merged to create a third list of routing layers. The net is assigned to one or more routing layers selected from the third list for routing purposes.

Resistance and capacitance aware preferred layer trimming

Aspects of the present disclosure address systems and methods for timing-based layer assignment. Routing is performed on a set of nets of an integrated circuit design. The routing comprises generating a route between a first pin and a second pin of a net. An initial layer assignment is performed on the set of nets based on the routing. The initial layer assignment comprises assigning the route to a first layer of the design based on first preferred routing layer designation. Timing-based layer assignment is performed based on the initial layer assignment. The timing-based layer assignment comprises reassigning the route from the first layer to a second layer based on a second preferred routing layer designation determined based on a comparison of a first delay value associated with the first layer and a second delay value associated with the second preferred routing layer designation.

Timing-based layer assignment

Aspects of the present disclosure address systems and methods for density-aware layer assignment for integrated circuit (IC) designs. Data describing an IC design is accessed. The IC design comprises a net and a set of routing layers. Single-layer routing and an initial layer assignment is performed on the set of nets. The single-layer routing and the initial layer assignment comprises generating a route for a net from the set of nets and assigning the route to one or more layers from the set of layers. A multi-layer density map is generated based on the single-layer routing and the initial layer assignment on the set of nets. Incremental layer reassignment is performed on the set of nets based on the multi-layer density map. The incremental layer assignment comprises reassigning a segment of the route from the first layer to a second layer from the set of layers based on the density value.

Wire density-aware layer assignment

Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

Routing congestion based on fractional via cost and via density

Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

Routing using rule-based blockage extension

Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

Layer assignment based on wirelength threshold

Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

Layer assignment and routing based on resistance or capacitance characteristic

Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Routing congestion based on layer-assigned net and placement blockage

Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising a source, a plurality of sinks, and a skew threshold associated with the source and the plurality of sinks. An initial routing tree is generated between the source and the plurality of sinks, and then a first intermediate point is identified between the source and the plurality of sinks. The first intermediate point may be identified based on a median location of all sinks of the plurality of sinks, or other criteria. The first intermediate point is then used for an updated routing tree. In some embodiments, a process proceeds iteratively until the skew threshold is reached or a maximum wire length is exceeded.

Routing tree topology generation

The present disclosure relates to a system and method for evaluating spanning trees. Embodiments may include receiving, using at least one processor, a spanning tree including one or more sinks coupled by one or more edges. Embodiments may further include receiving a user-selected floating parameter. Embodiments may also include interchanging the one or more edges of the spanning tree based upon, at least in part, the user-selected floating parameter.

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Austin, TX, United States of America

Derong Liu