Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Derek Stewart

Alan Kalitsov

Bhagwati Prasad

Gerardo Bertero

Michael Grobis

Bruce David Terris

Daniel Bedau

Ananth Kaushik

Christopher John Petti

Jeffrey Scott Lille

Matthew Joseph Carey

Kurt A Rubin

Ricardo Ruiz

Mac D Apodaca

Lei Wan

Goran Mihajlovic

John C Read

Young-Suk Choi

Tiffany Santos

Joyeeta Nag

A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.

Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

Voltage-controlled magnetic anisotropy memory device including an anisotropy-enhancing dust layer and methods for forming the same

Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.

Magnetoresistive memory device including a plurality of reference layers

A magnetoresistive memory device includes a first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes, from one side to another: a reference layer having a fixed reference magnetization direction, a first spinel layer located including a first polycrystalline spinel material having () texture along an axial direction that is perpendicular to an interface with the reference layer, a magnesium oxide layer including a polycrystalline magnesium oxide material having () texture along the axial direction, a second spinel layer including a second polycrystalline spinel material having () texture along the axial direction, and a ferromagnetic free layer.

Spinel containing magnetic tunnel junction and method of making the same

A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

Magnetic tunnel junction memory devices employing resonant tunneling and methods of manufacturing the same

A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Ferroelectric memory devices employing conductivity modulation of a thin semiconductor material or a two-dimensional charge carrier gas and methods of operating the same

A memory cell includes an ovonic threshold switch (OTS) selector containing a first electrode, a second electrode, an OTS located between the first electrode and the second electrode, and a current focusing layer containing discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS, and a memory device located in electrical series with the OTS selector.

Memory device containing selector with current focusing layer and methods of making the same

A magnetoresistive memory device includes first electrode, a second electrode that is spaced from the first electrode, and a perpendicular magnetic tunnel junction layer stack located between the first electrode and the second electrode. The perpendicular magnetic tunnel junction layer stack includes a first texture-breaking nonmagnetic layer including a first nonmagnetic transition metal, a second texture-breaking nonmagnetic layer including a second nonmagnetic transition metal, a magnesium oxide dielectric layer located between the first and second texture-breaking nonmagnetic layers, a reference layer located between the first and second texture-breaking nonmagnetic layers, a free layer located between the first and second texture-breaking nonmagnetic layers, and a spinel layer located between the reference layer and the free layer, and including a polycrystalline spinel material having (001) texture along an axial direction extending between the reference layer and the free layer.

A memory device includes a plurality of memory cells, and an isolation material portion located between the memory cells. The isolation material portion includes at least one ovonic threshold switch material portion.

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Livermore, CA, United States of America

Derek Stewart