Texas Instruments Corporation

Derek Roskell

Karl M Guttag

Richard D Simpson

Thomas A Dye

Michael D Asal

Jerry R Van Aken

Martin D Daniels

Neil Tebbutt

John V Schabowski

Brian Shore

Kevin C McDonough

Thomas Preston

Phillip Moyse

Marvin C Conrad

Jim A Carey

A maintenance circuit for a bus (1) with a tristate driver (2) which includes a keeper circuit (3) having a first inverting logic gate (4) with an input connected to the bus (1) and a second inverting logic gate (5) with an input (6) connected to the output of the first logic gate (4). The output of the second logic gate (5) is restricted in current relative to that of tristate driver (2) and is connected directly to the bus (1). The keeper circuit (3) has a control input (7) for disabling positive feedback therein, such that the keeper circuit (3) acts as a pull-up or pull-down circuit.

Bus maintenance circuit

A multiplier (220) selectively multiplies either a pair of 2N bit digital numbers or two pair of N bit digital numbers. The multiplier (220) includes a first input encoding circuit (350), a second input encoding circuit (352), a number of partial product generators (353, 354, 356, 363, 364, 366) and a set of adders (355, 357, 365, 367, 368, 369). The first input encoder circuit (350) generates partial product control signals from a first data word holding either a first 2N bit number or a first pair of N bit numbers. The second input encoding circuit (352) generates partial product input signals to the partial product generators (353, 354, 356, 363, 364, 366) from a second data word holding either a second 2N bit number or a second pair of N bit numbers. A first set of adders (355, 357) forms a weighted first sum of the first set of partial products signals. A second set of adders (365, 367) forms a weighted second sum of said second set of partial product signals. A third adder ( 368) forms a weighted sum of the first and second sums. The multiplexer (369) forms an output from the third adder in the 2N by 2N multiplication mode and forms an output having least significant bits corresponding to the first sum and most significant bits corresponding to the second sum in the pair of N by N multiplications modes.

Split multiply operation

A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user. Similarly, responsive instead to a load command, a routine is executed which presents the series of addresses to the memory bus and loads the internal registers with the data values presented on the memory bus. The load feature is similarly utilized by the user's loading of the addressed memory locations with the desired contents of the internal registers. A system containing a microprocessor constructed according to the invention may be configured so that the emulate enable signal is generated by the control signals generated by the microprocessor upon each instruction fetch from the external memory.

Data processing apparatus with self-emulation capability

A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes. An additional SRL is contained within each test port, and in the scan path, for storing a logic state corresponding to whether the functional circuitry in the module is to be connected to or disconnected from the system bus during the test sequence. A configuration is further disclosed which has global SRLs in the modules; such global SRLs are always in the scan path, regardless of whether or not the module containing them is selected. Multiplexing of the scan data and the configuration data is also disclosed.

Logic circuits systems, and methods having individually testable logic

A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes. An additional SRL is contained within each test port, and in the scan path, for storing a logic state corresponding to whether the functional circuitry in the module is to be connected to or disconnected from the system bus during the test sequence. A configuration if further disclosed which has global SRLs in the modules; such global SRLs are always in the scan path, regardless of whether or not the module containing them is selected. Multiplexing of the scan data and the configuration data is also disclosed.

Logic circuit having individually testable logic modules

A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.

Parallel binary adder having grouped stages including dynamic logic to

A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic '0' and '1'. In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic '0' to a logic '1' when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for a three quarter of a machine cycle to allow any transient conditions within the latch to dampen out.

Synchronizer circuit with dual input

A digital processing system includes an external memory for the storage of program instructions for use with a separate processor that internally contains a memory for temporary storage, an arithmetic and logic means, a register set, control and timing circuitry, and two sets of data paths. The first set of data paths provide access to the external memory for transfer of instructions from the external memory to the processing unit. The second set of data paths provide for the internal routing of instructions data and addresses within the processor unit itself. The data structure for the first set of data paths is different than that for the second set of data paths, providing for an external data structure that is different than the internal data structure of the processor.

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Northants, United Kingdom

Derek Roskell