Cypress Semiconductor Corporation

Derek R Johnson

Mathew R Arcoleo

Raymond M Leong

Jonathan F Churchill

A memory array comprising a plurality of storage elements and a logic circuit. The memory array may be configured to (i) receive a plurality of input data streams, (ii) store each of the plurality of input data streams in one or more of the storage elements in response to a plurality of control signals and (iii) present a plurality of output data streams in response to the plurality of input data streams. The logic circuit may present the plurality of control signals in response to the fullness of each of the plurality of storage elements.

Cascadable multi-channel network memory with dynamic allocation

An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device. Since the output buffer circuit of the invention allows the output buffer drive strength to be more closely tailored to the electrical load being driven, signal reflections, voltage overshoot and undershoot, and timing problems that can result from mismatch between the output buffer drive strength and the associated electrical load can be reduced.

Memory having selectable output strength

A Static Random Access Memory (SRAM) comprises an input/output pin and driver means connected to the input/output pin. The driver means are configured to drive the input/output pin to a voltage potential using a first current, and are further configured to hold the input/output pin at approximately the voltage potential using a second current. In one embodiment, the driver means may comprise a driver unit for driving the input/output pin to the voltage potential, a bus hold circuit for holding the input/output pin at the voltage potential and a control unit connected to the driver unit and the bus hold circuit. The control unit may activate and deactivate the driver unit and the bus hold circuit.

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Los Gatos, CA, United States of America

Derek R Johnson