Apple Inc.

Derek Fujio Iwamoto

Joseph P Bratt

Sushma Shrikant Trivedi

Jack Benkual

Jorge L Rivera Espinoza

Venkatesh Rajendran

Brijesh Tripathi

Shane J Keil

Michael J Smith

Josh P De Cesare

Vaughn Todd Arnold

Erik G De Jong

Keith Alan Cox

Manu Gulati

Parin Patel

Cyril De La Cropte De Chanterac

Lynn Richard Youngs

William C Lukens

Steven C Roach

Ronald Ray Hochsprung

Christopher J Young

William O Ferry

Neeloy Roy

Yue Chen

Scott D Morrison

Siddharth Nangia

Steven Todd Weybrew

Xiaofang Mu

Christopher D Guichet

Patrick J Crowley

Yi-Chun Chen

David Ligon

Woojin Jung

Yutaka Takahashi

Mark Ferdinand Damarillo

Itay Franko

Kevin A Klenk

Zhiwei Gu

Annie Manuja

A host device establishes a wireless communication link with a client device, and implements a wired communication standard on the link to transfer a first data stream. To increase data throughput while complying with the standard, the host device replaces synchronizing information in a packet to be sent during a first synchronizing frame with configuration information indicating that packet exchange data of a second data stream is to be sent or received during a second synchronizing frame. The host device sends or receives the packet exchange data of the second data stream to or from the client device during the second synchronizing frame via the wireless communication link. The host device may send or receive the packet exchange data of the second data stream during delays or idle periods between sending and/or receiving packets of the first data stream via the wireless communication link according to the wired communication standard.

Aggregating multiple data streams on a communication link

A wireless communication system may include an electronic device having a wireless communication module. The wireless communication module may include an antenna radiating element on a first surface, a ground ring surrounding the antenna radiating element on the first surface, and a radio component mounted to a second surface. The wireless communication module may be incorporated into a system package that also includes other components. Encapsulation material may cover the wireless communication module and other components. A shielding material may cover the encapsulation material and be coupled to the ground ring. An opening in the shielding material may be aligned with the antenna radiating element. If desired, the wireless communication system may include external equipment having a wireless communication module communicatively coupled to the wireless communication module to convey firmware testing, debugging, restore, and/or other data.

Wireless communication devices

Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Mechanism for saving power on a bus interface

An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Interface emulator using FIFOs

Method and apparatus of emulating interfaces using FIFOs

A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Method and apparatus for providing telemetry for power management functions

Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.

Method and apparatus for data processing

Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.

Method and apparatus for forming and dispatching instruction groups based on priority comparisons

A memory unit is described that has a controller coupled to a memory core through an interface circuit. The interface circuit has a test data input that receives test data from the controller. The interface circuit also has a system data input that receives data from a system. The interface circuit has a data output that is coupled to a data input of the memory core.

Method and apparatus for improved memory core testing

At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

Memory controller chipset

Growing community of inventors

San Jose, CA, United States of America

Derek Fujio Iwamoto