Microsoft Technology Licensing, LLC

Derek E Gladding

Amar Vattakandy

Robert W Havlik

Michael J Erickson

Xiaoling Xu

Smitha L Rapaka

Shankar S Narayan

Nitin Garegrat

Xin Huang

Sunil Kumar Vemula

Venkatesh Balasubramanian

Michael Stephen Sterling

Bartosz Tomasz Nyczkowski

Cesar Maldonado

Sujatha Santhanaraman

Sudharsan Gopalakrishnan

Hsu-Kuei Lin

Jayadev Velagandula

Shaileshkumar D Kumbhani

An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Activity smoothener circuit controlling rates of change of localized processing activity in an integrated circuit (IC), and related methods

A command queue is configured to receive a command from a software application. A configuration storage is configured to store a plurality of configurations. A matrix multiplication unit is configured to perform matrix multiplication operations. Memory is configured to store matrices. A control engine is configured to retrieve the command from the command queue; retrieve a configuration from the configuration storage based on the command; generate, based on the command and the configuration, instructions for the matrix multiplication unit to perform a set of matrix multiplication operations on first and second matrices stored in the memory; send the instructions to the matrix multiplication unit to configure the matrix multiplication unit to output results of the set of matrix multiplication operations; and store the results in a third matrix in the memory.

Performing tensor operations using a programmable control engine

Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Processor-based system employing configurable local frequency throttling management to manage power demand and consumption, and related methods

Embodiments of the present disclosure include systems and methods for storing tensors in memory based on depth. In some embodiments, for each of a plurality of sets of elements in a three-dimensional (3D) matrix, a position is determined along a height axis and width axis of the 3D matrix. At the determined position, a set of elements are identified along a depth axis of the 3D matrix. The set of elements are stored in a contiguous block of memory.

Storing tensors in memory based on depth

Innovations in range asymmetric number system ('RANS') coding and decoding are described herein. Some of the innovations relate to hardware implementations of RANS decoding that organize operations in two phases, which can improve the computational efficiency of RANS decoding. Other innovations relate to adapting RANS encoding/decoding for different distributions or patterns of values for symbols. For example, RANS encoding/decoding can adapt by switching a default symbol width (the number of bits per symbol), adjusting symbol width on a fragment-by-fragment basis for different fragments of symbols, switching between different static probability models on a fragment-by-fragment basis for different fragments of symbols, and/or selectively flushing (or retaining) the state of a RANS decoder on a fragment-by-fragment basis for different fragments of symbols. In many cases, such innovations can improve compression efficiency while also providing computationally efficient performance.

Features of range asymmetric number system encoding and decoding

A method for providing in-place safe decompression of a data stream includes utilizing a stored offset to allocate a memory space for a decompression operation. The stored offset represents a maximum offset by which a write pointer position of an output stream exceeds a read pointer position for a corresponding input stream during in-place decompression of the compressed data stream.

In-place safe decompression

Data compression schemes may indicate the length of the compressed data block in a header or in the compressed data itself. If the start and end of the data block are known before the decoding process has completed by the decoding stage, a header processing stage can 'skip ahead' to the start of the next block to begin processing the header of the next block while the current block is still being decoded. Thus, the header processing stage and the decoding stage are operated concurrently. If the end of the compressed block is indicated in the compressed data itself the end of the data block is not known until the end of the compressed data block is reached. For these types of compressed data blocks, the header processing stage waits until the decoding stage finishes with the preceding block before processing the header of the current block.

Multi-format pipelined hardware decompressor

Decompressing sliding window compressed data requires reference to previously decompressed character sequences. Previously decompressed data is stored in a history buffer to satisfy these 'back references.' As each decompressed/decoded character is emitted, it is stored in this history buffer. Thus, for each decompressed character that is emitted, the history buffer may need to be accessed at least twice&#x2014;once to retrieve the backreference, and once to store the emitted character. A pipeline architecture is disclosed that stores decompressed characters in a write queue that coalesces eight or more emitted characters before they are stored in the history buffer memory. This reduces collisions between accessing the history buffer memory to retrieve the backreferences and the storing of the emitted character. This also allows the use of a single-ported memory which is less expensive than a multi-ported memory.

Pipelined decompression of sliding window compressed data

In some data compression algorithms and/or standards, the compressed data comprises variable length symbols. A set of parallel decoders speculatively decode/decompress a window (i.e., sub-block) of data. Each of the decoders attempts to decode/decompress a symbol that starts at a different location in the compressed data block. Once the decoders have finished decoding a symbol (or determined that a valid symbol does not begin at the beginning of the window assigned to that decoder), a symbol strider selects the decoder outputs corresponding to valid symbols. The symbol strider successively selects decoder outputs based on the size of the previous symbols that were found to be valid. When the next valid symbol begins outside the current window, its location is stored to indicate the location of the next valid symbol in a subsequent window.

Multi-symbol, multi-format, parallel symbol decoder for hardware decompression engines

To decompress encoded data, a Huffman code tree stored in a data header may need to be decompressed and rebuilt. A bit length histogram table is used in a hardware design to more efficiently decompress the Huffman code tree. The bit length histogram table relates each bit length used by the Canonical Huffman Code (CHC) symbols to a corresponding number of symbols in the encoding that have that bit length. Performing decompression using bit length histogram table allows part of the Huffman tree decompression to be performed in a single pass.

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Pacifica, CA, United States of America

Derek E Gladding