International Business Machines Corporation

Derek Chen

Huilong Zhu

David V Horak

Wesley Charles Natzle

Chienfan Yu

Sadanand Vinayak Deshpande

Scott W Crowder

Hung Y Ng

Len Yuan Tsou

William M Chu

Frederick William Buehrer

A flash memory device includes a wafer; a gate oxide layer disposed upon the wafer; a floating gate disposed upon the gate oxide layer, the wafer, or a combination thereof; the floating gate including a flat floating gate portion and a generally rectangular floating gate portion disposed upon selected areas of the flat floating gate portion; a high K dielectric material disposed upon the floating gate; and a control gate disposed upon the high K dielectric material; wherein the high K dielectric material forms a zigzag pattern coupling the floating gate with the control gate.

High performance flash memory devices

A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.

Vapor phase etch trim structure with top etch blocking layer

Growing community of inventors

Mount Kisco, NY, United States of America

Derek Chen