Taiwan Semiconductor Manufacturing Comp. Ltd.

Derek C Tao

Kuoyuan (Peter) Hsu

Yukit Tang

Annie-Li-Keow Lum

Jacklyn Chang

Bing Wang

Chung-Ji Lu

Young Seog Kim

Annie Lum

Cheng Hung Lee

Hong-Chen Cheng

Young Suk Kim

Kuoyuan Hsu

Vineet Kumar Agrawal

Keun-Young Kim

Shaojie Xu

Pyong Yun Cho

Pao-Po Hou

Hung-Jen Liao

Chan-Hong Chern

Chih-Chang Lin

Ming-Chieh Huang

Tao Wen Chung

Tsung-Ching Huang

Kuo-Yuan Hsu

Dong Sik Jeong

Kai Fan

Allen Fan

Subramani Kengeri

Jung-Ping Yang

Yong Zhang

Dongsik Jeong

Evan Yong Zhang

Jay Lu

Chungjz Lu

Liang-Yu Chen

A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein.

Semiconductor device

A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Method of fabricating a semiconductor device

A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.

A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other.

Memory metal scheme

A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Modified design rules to improve device performance

A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Timing delay characterization method, memory compiler and computer program product

Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.

Rule based data normalization utilizing multi-key sorting

A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.

Memory with regulated ground nodes and method of retaining data therein

A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.

A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

Method and control circuit for memory macro

In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.

Reading data from a memory cell

A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.

Method of writing memory with regulated ground nodes

A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.

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Fremont, CA, United States of America

Derek C Tao