Nxp Usa, Inc.

Freescale Semiconductor,inc.

Derek Beattie

Robert Freddie Moran

Carl Culshaw

James Andrew Collier Scobie

Andrew Edward Birnie

Mark Maiolani

Alan Devine

Deboleena Sakalley

Norbert Pickel

Axel Bahr

Andrew E Birnie

Gary L Miller

James Robert Feddeler

Alistair Robertson

Rakesh Pandey

Ray Charles Marshall

Alistair James Gorman

Jeffrey Thomas Loeliger

Gordon James Campbell

Mark Jordan

Stephen McGinty

Gordon Campbell

An automotive control system includes a safety processor and a system-on-a-chip. The SoC includes a primary processor, a safety monitor, first and second GPIO banks, and a debug interface. The safety monitor is configured to detect a fault condition of the primary processor and to provide an indication of the fault condition to the safety processor. The first GPIO bank is coupled to the primary processor to provide input/output operations to a non-critical function of an automobile, while the second GPIO bank is coupled for a critical function of the automobile. The debug interface is coupled to the second GPIO bank to form a scan chain with input and output registers of the second GPIO bank, and is coupled to the safety processor to receive control information for the scan chain to provide input/output operations to the critical function of the automobile when the safety monitor provides the indication.

System and method to provide safety partition for automotive system-on-a-chip

An integrated circuit (IC) module comprising at least one memory mapped resource, at least one port arranged to be coupled to a further IC module, and an address decoding component. Upon receipt of a resource access request by the IC module, the address decoding component is arranged to extract at least one position parameter from an address field of the received resource access request, determine if the at least one position parameter indicates a target resource as residing within the IC module, and if it is determined that the at least one position parameter indicates the target resource as not residing within the IC module, modify the at least one position parameter to represent a change of one position and forward the resource access request with the modified position parameter over the port to the further IC module.

IC module and method of decoding resource access requests

A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration.

Micro controller unit including an error indicator module

Aspects of the invention relate to an integrated circuit device and method of production thereof. The integrated circuit device comprises at least one application semiconductor die comprising at least one functional component arranged to provide application functionality, at least one functional safety semiconductor die comprising at least one component arranged to provide at least one functional safety undertaking for the at least one application semiconductor die, and at least one System in Package, SiP, connection component operably coupling the at least one functional safety semiconductor die to the at least one application semiconductor die to enable the at least one functional safety semiconductor die to provide the at least one functional safety undertaking for the at least one application semiconductor die.

Integrated circuit device

An apparatus for maintaining alertness of an driver of a motor vehicle periodically generates an audible alert signal to which the driver responds by pressing a button on the vehicle's steering wheel. The response time of the driver to the signal is monitored and if an increase is detected, the repetition rate of the alert signal is increased. The repetition rate may be further modified by taking into account vehicle driving conditions which may indicate a risk of boredom in the driver.

Method and apparatus for maintaining alertness of an operator of a manually-operated system

A method and apparatus for generating an indicator of a risk level in motor vehicle and notifying vehicle systems when a risk level is above a specific threshold includes, receiving a plurality of driver distraction indicators, assigning a weighting value to each indicator, applying a scaling factor to the weighting value assigned to those indicators which are identified as being related, and summing the weighting values to produce an output value indicating a risk level. Distraction indicators can include on-board system and sensor outputs and stored data relating to driver attributes. Related indicators may comprise those distraction indicators relating to environmental conditions (eg. rain and low ambient light levels), or to vehicle performance to driver concentration level (eg. in-car phone and navigation system). The scaling step allows the weighting process to be refined based on the status of other received indicators.

Method and apparatus for generating and indicator of a risk level in operating systems

A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.

End-to-end error detection and correction

A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface. The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface. The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system

There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules. There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.

Semiconductor wafer and method of fabricating an IC die

A system in a package (SiP) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package. The nonvolatile memory of the first semiconductor die is configured to store trim/repair values for each of the first and the second semiconductor die. The trim/repair circuitries of the first and second semiconductor die are configured to, in response to a reset of the second semiconductor die, copy the trim/repair values from the nonvolatile memory of the first semiconductor die to the volatile memory of the second semiconductor die.

System in a package (SiP)

A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

Method, system and integrated circuit for enabling access to a memory element

A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Multi-core clocking system with interlocked 'anti-freeze' mechanism

A microcontroller unit comprises a reset controller operably coupled to a plurality of logic elements of the microcontroller unit. Low voltage detection logic is operably coupled to the reset controller and arranged to provide a plurality of low voltage interrupt signals to a number of respective logic elements of the microcontroller unit via the reset controller. A method of operating a microcontroller unit is also described.

Microcontroller unit and method therefor

A method for programming/erasing a non-volatile memory (NVM) includes performing a program/erase operation on a portion of the NVM using a first set of parameters. The method further includes determining whether each cell in the portion of the NVM passes a first margin level, if not determining which one of a set of lower margin levels than the first margin level each cell in the portion of the NVM passes. The method further includes modifying at least one of the set of parameters associated with a subsequent program/erase operation for the portion of the NVM based on the determined one of the set of lower margin levels.

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Glasgow, United Kingdom

Derek Beattie