Intel Corporation

Derek B Feltham

David Zimmerman

Jonathan P Douglas

Michael W Rhodehamel

Tak Ming Mak

Christopher J Nelson

Anthony C Miller

Adrian L Carbine

James A Wilson

Sumeet Agrawal

Ray Ramadorai

I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.

Input/output delay testing for devices utilizing on-chip delay generation

In some embodiments, a method and apparatus for disabling and swapping cores in a multi-core microprocessor are presented. In this regard, a test agent is introduced to disable a core, to configure a mode, and to configure a site. Other embodiments are also disclosed and claimed.

Method and apparatus for disabling and swapping cores in a multi-core microprocessor

A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

Control register bus access through a standardized test access port

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Portland, OR, United States of America

Derek B Feltham