Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Derek Alan Sherlock

Gregg Bernard Lesartre

Harvey Ray

Gary Belgrave Gostin

Shawn Kenneth Walker

Nicholas George McDonald

Frank R Dropps

Paolo Faraboschi

Darel N Emmot

Michael Kontz

Mark David Lillibridge

Russ William Herrell

Thomas V Spencer

Alan Lynn Davis

Chris Michael Brueggen

Matthew B Lovell

Jayen J Desai

Christopher Michael Brueggen

Joseph George Tietz

Joe Perry Cowan

Francisco Corella

Christopher Shawn Kroeger

Al Davis

Timothy Pertuit

John Kim

Chih-Jen Chen

Alan Pippin

Daniel P Carrington

Darel Nea Emmot

A switching fabric uses traffic congestion information to inform its opportunistic use of non-minimal routes. An ingress port of a network switch collects traffic congestion information from the egress ports of the network switch. The traffic congestion information includes minimal and non-minimal route congestion metrics for the egress ports. Candidate egress ports for forwarding a packet to a destination node are identified. One of the candidate egress ports is selected based on the traffic congestion information. The selection process is biased to prefer some candidate egress ports over others. Particularly, the candidate egress ports that provide non-minimal routes to the destination node and have high minimal route congestion metrics are disfavored by the selection process.

Multipath routing for switching fabric

One aspect of the instant application can provide a networking device. The networking device can include a set of Compute Express Link (CXL) ports, a set of non-CXL ports, a set of bridge circuits associated with the set of CXL ports, and an interconnect. A respective bridge circuit can include a packet-conversion subcircuit to convert a CXL packet received at a corresponding CXL port to a customized packet and a protocol-conversion subcircuit to convert a CXL protocol to a customized protocol implemented by the networking device. The interconnect can switch customized packets among the CXL and non-CXL ports based on the customized protocol.

CXL fabric extensions

One aspect of the instant application can provide a storage system. The storage system can include a plurality of byte-addressable storage devices and a plurality of media controllers. A respective byte-addressable storage device is to store a parity block or a data block of a data stripe, and a respective media controller is coupled to a corresponding byte-addressable storage device. Each media controller can include a tracker logic block to serialize critical sections of multiple media-access sequences associated with an address on the corresponding byte-addressable storage device. Each media-access sequence comprises one or more read and/or write operations, and the data stripe may be inconsistent during a critical section of a media-access sequence.

Simplified raid implementation for byte-addressable memory

A system for facilitating efficient progression management in a multi-source tracker of a responder device is provided. During operation, the system can maintain, in a memory device of the responder device, a first tracker for all requests and a second tracker for a privileged group of requests. The system can select a first group from a set of groups as the privileged group. If a request from a requesting device cannot be accepted into the first tracker, the system can determine whether the request belongs to the first group based on a header field of the request. If the request belongs to the first group, the system can select the request for accepting into the second tracker. Subsequently, when a respective request belonging to the first group has been accepted, the system can select a second group from the set of groups as the privileged group.

Efficient progression management in a tracker with multiple sources

A system for facilitating enhanced virtual channel switching in a node of a distributed computing environment is provided. During operation, the system can allocate flow control credits for a first virtual channel to an upstream node in the distributed computing environment. The system can receive, via a message path comprising the upstream node, a message on the first virtual channel based on the allocated flow control credits. The system can then store the message in a queue associated with an input port and determine whether the message is a candidate for changing the first virtual channel at the node based on a mapping rule associated with the input port. If the message is a candidate, the system can associate the message with a second virtual channel indicated in the mapping rule in the queue. Subsequently, the system can send the message from the queue on the second virtual channel.

Enhanced virtual channel switching

A system includes a central processing unit (CPU) to process data with respect to a virtual address generated by the CPU. A first memory management unit (MMU) translates the virtual address to a physical address of a memory with respect to the data processed by the CPU. A supervisory MMU translates the physical address of the first MMU to a storage address for storage and retrieval of the data in the memory. The supervisory MMU controls access to the memory via the storage address generated by the first MMU.

Supervisory memory management unit

A communications device that includes a requester and a responder may support multiple transaction classes, including an ordered transaction class, while maintaining a bifurcated requester/responder architecture. Before a responder has a non-posted transaction response to transmit on an interconnect, it receives an indication from the requester that there is not a pending posted transaction on the interconnect.

Device supporting ordered and unordered transaction classes

One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

System and method for tracking persistent flushes

In some examples, a tracker receives a write request that is acknowledged upon receipt by a destination media controller without waiting for achievement of persistence of write data associated with the write request. The tracker adds an identifier of the destination media controller to a tracking structure in response to the identifier not already being present in the tracking structure. The tracker sends a request to persist write operations to media controllers identified by the tracking structure.

Tracking write requests to media controllers

A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

Mapping entry invalidation

A method for evaluating an electronic design under test may be performed in an environment that includes a functional verification test bench having at least one verification component coupled to the electronic design under test. The method includes provisioning the functional verification test bench to provide protocol-agnostic performance data for activity of the electronic design under test during functional verification testing of the electronic design under test. The method further includes capturing at least a part of the protocol-agnostic performance data from the at least one verification component, and calculating, from the protocol-agnostic performance data, a performance measurement for the electronic design under test.

Performance evaluation for an electronic design under test

According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

Serializing access to fault tolerant memory

Example implementations relate to congestion management across a network fabric. An example implementation includes setting an uncongested sequence length threshold to a first value. A completed transaction received count may also be set to an initial value. The completed transaction received count may be incremented in response to a completion of a transaction request. In response to a detected congestion event, the injection rate may be decreased. A second value for the uncongested sequence length threshold may be determined from the CTR count, and the uncongested sequence length threshold may be set to the second value. Furthermore, in response to the CTR count being greater than or equal to the uncongested sequence length threshold, the injection rate may be increased.

Network congestion management

A method may include receiving a first transaction request. The method may further include transmitting a retry response to the transaction request, which includes a first epoch identifier associated with a current epoch. The method may further include receiving a second transaction request, which includes a second epoch identifier associated with a previous epoch. The second transaction request may be fulfilled using a transaction resource reserved for the previous epoch.

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Fort Collins, CO, United States of America

Derek Alan Sherlock