Intel Corporation

Derek A Thompson

Darrell S McGinnis

Steve A McKinnon

John F Zumkehr

In some embodiments, a system and method for mapping the logical chip selects to a physical chip select. A chip select remapping unit receives logical chip select associated with a dual in-line memory module. The chip select remapping unit converts the logical chip select vector through a redirection table that maps the logical memory ranks to available physical memory ranks.

Logical to physical address mapping of chip selects

In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required &#xbc; clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.

System and method for dynamic rank specific timing adjustments for double data rate (DDR) components

Write pointer error recovery systems and methods are provided. A write pointer from a write pointer circuit may cause a demultiplexer circuit to direct data from a memory cell to a desired bit location in a register. A read pointer may cause a multiplexer circuit to select data from a desired bit location in the register to provide as output data or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal. The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line. Other embodiments are also claimed and described.

Write pointer error recovery systems and methods

A write pointer () from a write pointer circuit () may cause a demultiplexer circuit () to direct data from a memory cell (A&#x2013;N) to a desired bit location () in a register 14. A read pointer () may cause a multiplexer circuit () to select data from a desired bit location in the register to provide as output data () or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal (). The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line ().

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Portland, OR, United States of America

Derek A Thompson