International Business Machines Corporation

Dereje G Yilma

Timothy Joseph Schmerbeck

Patrick Lee Rosno

Raymond Alan Richetta

Eric John Lukes

Glen Arthur Wiedemeier

Matthew James Paschal

Nghia Van Phan

Chad Andrew Marquart

Brent Ray Den Hartog

Christopher W Steffen

Erik English

Michael Wayne Harper

Jeffrey Kwabena Okyere

Venkat Harish Nammi

Vikram B Raj

Nathan Ross Blanchard

Daniel Mark Dreps

David Michael Friend

Yang You

Michael Robert Curry

Richard Scott Brink

James Crugnale

Donald R Fearn

Ze Zhang

A power saving improvement in an injection locked oscillator (ILO) used is described. The ILO circuitry comprises a feedback path to provide a finecal (M-bit fine calibration signal). The feedback path need not be active at all times; only when an event occurs that requires the feedback path to update the value of the finecal signal. A monitor is provided to sense the occurrence of such event which may be, for examples, an end of a time period or a predetermined change in temperature. When the event occurs, the feedback path is activated to update the value of the finecal signal.

Multi-phase clock generation circuit with digital calibration

Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

High-speed deserializer with programmable and timing robust data slip function

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers

Aspects of the invention include a driver arranged at a stand-alone receiver that is configured to receive a binary sequence from a pseudorandom binary sequence (PRBS) generator arranged at the receiver. The driver is configured to adjust the signal characteristics of the binary sequence to simulate channel loss at the receiver. The driver is further configured to output the adjusted binary sequence to a downstream data path of the receiver to enable the receiver to perform a self-test.

Built-in-self-test and characterization of a high speed serial link receiver

A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a first active dummy FET that shares the source region and that also has a diffusion region. The row may also contain a second active FET and a second active dummy FET, positioned such that the active dummy FETs are located between the active FETs on the row. The row may also have an end positioned such that the first active dummy FET is between the end and the first active FET. A supply of current may be electrically connected to the source diffusion regions. A load region may be electrically connected to the drain region. The first active FET and the first active dummy FET may have gates that share a voltage source or that have their own voltage source.

Field effect transistor structure for reducing contact resistance

Certain aspects of the present disclosure are directed to a circuit for driving a signal at an output node. The circuit generally includes a voltage divider network having a first terminal coupled to the output node. The circuit also includes a first transistor having a gate coupled to a second terminal of the voltage divider network and a plurality of transistors. A gate of each of the plurality of transistors may be coupled to a respective tap node of the voltage divider network, and the plurality of transistors may include a third transistor having a source coupled to a drain of the first transistor. The circuit may also include a second transistor coupled to the first transistor and having a gate coupled to an input node of the circuit.

Bidirectional interface using thin oxide devices

A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject circuit resides. Peak detectors are used to detect a positive or up level reached by a resonant clock and negative or down level reached by the resonant clock. Each detected levels is compared to a reference level to determine when to vary the turn off timing of a clock driver pull-up device and/or a clock driver pull-down device. A positive peak detector controls the turn off time of the pull-up device and a negative peak detector controls a turn off time of the pull-down device in the pulsed resonant driver.

Implementing adaptive control for optimization of pulsed resonant drivers

A gated differential logic circuit can include a header device having a first terminal coupled to a supply voltage, and a second terminal; a second header device having a third terminal coupled to the supply voltage, and a fourth terminal; a footer device having a fifth terminal coupled to ground, and a sixth terminal; and a second footer device having a seventh terminal coupled to ground, and an eighth terminal. The circuit further includes a driver circuit having a first supply terminal coupled to the second terminal and a first ground terminal coupled to the sixth terminal, and a second driver circuit having a second supply terminal coupled to the fourth terminal and a second ground terminal coupled to the eighth terminal. A capacitor can couple the first supply terminal to the second ground terminal, while a second capacitor may couple the second supply terminal to the first ground terminal.

Gated differential logic circuit

The present invention provides a power saving method and apparatus for powering a lower voltage device from a higher voltage power source. The apparatus includes a switch having an input coupled to an output of the higher voltage power source. The apparatus further includes a high-to-low voltage converter having an input coupled to an output of the switch. The apparatus also includes a power plug having an input coupled to an output of the high-to-low voltage power converter, and an output configured to receive a power socket of the low voltage device. Finally, the apparatus includes a switch actuator coupled to the power plug and the switch. When the power plug is operatively engaged within the power socket of the lower voltage device, the switch actuator closes the switch. When the power plug is operatively disengaged from the power plug, the switch actuator opens the switch.

Energy savings for a system powering a lower voltage device from a higher voltage power source, and wherein the system includes a power plug that outputs power to a converter, and a switch actuator

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Rochester, MN, United States of America

Dereje G Yilma