Intel Corporation

Micron Technology Incorporated

Stmicroelectronics S.r.l.

Ovonyx Inc.

Derchang Kau

Gianpaolo Spadini

Rajesh Sundaram

Jong-Won Sean Lee

Kiran Pangal

Shekoufeh Qawami

Balaji Srinivasan

Raymond W Zeng

Davide Mantegazza

Hernan Adolfo Castro

Stephen W Russell

Jong Won Lee

Feng Q Pan

Stephen H Tang

Albert Fazio

Owen W Jungroth

Daniel Chu

Davide Fugazza

Johannes A Kalb

Charles C Kuo

Sandeep K Guliani

Mase J Taub

Doyle W Rivers

Prashant S Damle

Khaled Hasnat

Matthew Goldman

Everett B Lee

Gerard H Joyce

Ashir G Shah

Charles H Dennison

Fabio Pellizzer

Innocenzo Tortorelli

Andrea Redaelli

Agostino Pirovano

Prashant Majhi

Elijah V Karpov

John Heck

Max F Hineman

Haisheng Rong

David Zimmerman

Jeremy Miles Hirst

Richard Keith Dodge

Shafqat Ahmed

Jeffrey B Driscoll

Harel Frish

Jonathan K Doylend

Dany-Sebastien Ly-Gagnon

Timothy C Langtry

Henry Chao

Brett E Klehn

George A Ghiurcan

Michael E Favaro

Brett Klehn

A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure further includes a pair of memory cells, where individual ones of the memory cells includes a selector and a memory element, where a first terminal of the individual ones of the memory cell is coupled to a respective second and a third terminal of the first interconnect. A second terminal of the individual ones of the memory cell is coupled to individual ones of the pair of second interconnects.

Pillar select transistor for 3-dimensional cross point memory

A memory device including a three dimensional crosspoint memory array comprising memory cells each comprising two terminals and a storage element programmable to one of a plurality of program states each representing distinct values for at least two bits; and access circuitry to apply a first program pulse with a positive polarity across the two terminals of a first memory cell of the memory cells to program the first memory cell to a first program state of the program states; and apply a second program pulse with a negative polarity across the two terminals of the first memory cell to program the first memory cell to a second program state of the program states.

Multi-level memory programming and readout

A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

Bipolar decoder for crosspoint memory

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.

Self-aligned cross-point phase change memory-switch array

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

A method, apparatus and system to address memory cells in a memory array that includes address lines comprising wordlines (WLs) and bitlines (BLs). The method comprises: controlling a decoder circuitry of a memory array, the memory array including a plurality of WLs and a plurality of BLs, the decoder circuitry including a plurality of switches coupled respectively to the WLs, or respectively to the BLs; and causing a selected switch of the plurality of switches to change a bias of a corresponding selected address line coupled thereto from a floating bias at an idle state of the decoder circuitry to either a positive bias or a negative bias without changing a bias at deselected address lines corresponding to deselected switches of the plurality of switches from the floating bias at the idle state.

Device, system and method to float a decoder for deselected address lines in a three-dimensional crosspoint memory architecture

A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.

Bipolar decoder for crosspoint memory cells

Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

Scalable bandwidth non-volatile memory

Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a substrate, a waveguide disposed above the substrate, a phase change layer disposed above the waveguide, and a heater disposed above the phase change layer. The waveguide has a modifiable refractive index based at least in part on a state of a phase change material included in the phase change layer. The phase change material of the phase change layer is in a first state of a set of states, and the waveguide has a first refractive index determined based on the first state of the phase change material. The heater is to generate heat to transform the phase change material to a second state of the set of states, and the waveguide has a second refractive index determined based on the second state of the phase change material. Other embodiments may also be described and claimed.

Semiconductor photonic devices using phase change materials

Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.

Apparatuses and methods including memory access in cross point memory

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

Replacement materials processes for forming cross point memory

Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

Apparatuses for modulating threshold voltages of memory cells

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Cupertino, CA, United States of America

Derchang Kau