United Microelectronics Corp.

Der Yuan Wu

Water Lur

Jiun Y Wu

Jiunn Y Wu

Ming-Tsung Liu

Shih-Chanh Chang

A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds. The final step is to release the system stress by tempering the layer at a temperature of between about 600.degree. to 750.degree. C. This completes the barrier layer which has good adhesion to the dielectric layer(s) and, therefore, promotes improved pad bonding yield.

Method of making a reliable barrier layer

A field oxide structure having a reduced number of defects is described. A field oxide mask is formed over a substrate having openings which expose portions of the substrate where the field oxide structures are to be formed. Silicon nitride spacers are formed on the sidewalls of the openings. Channel stop ions are selectively implanted through the opening into the substrate and then the thick field oxide structures are formed. Stress-generated crystalline defects are formed underlying the field oxidation regions at the edges of the openings. The silicon nitride spacers are removed. An additional source/drain ion implantation is performed by implanting ions to doped regions in the substrate deep enough into the substrate so that the crystalline defects are enclosed within the implanted regions to reduce junction leakage. The silicon dioxide, silicon nitride, and pad silicon oxide layers are removed to complete the field oxide structure.

Locos technology with reduced junction leakage

In the fabrication of VLSI circuits, the diffusion barrier layer on the pad areas are removed prior to the formation of metal layer. Metal layer on the pad areas are thus directly contact with the underlying SiO.sub.2 layer, thereby improving the pad bonding yield.

Growing community of inventors

Hsin-Chu, Taiwan

Der Yuan Wu