Solarflare Communications, Inc.

Divio, Inc.

Sun Microsystems, Inc.

Marvell Asia Pte., Ltd.

Ess Technology, Inc.

Level 5 Networks, Inc.

Der-Ren Chu

David James Riddoch

Derek Edward Roberts

Ching Yu

John Mingyung Chiang

Steve Leslie Pope

Ren-Yuh Wang

Sophia Wei-Chun Kao

Steven Leslie Pope

Kang-Huai Wang

Cong Quoc Khieu

Hon Wai Fung

Lan Lee

Liang Zhu

Xin Liu

Ming-Tak Leung

Chia-Hung Chen

Wei-Chun Lee

Tony Hung-Yao Wu

Bizhan Abedinzadeh

Steve L Pope

Derek Roberts

A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.

Sleep and wakeup signaling for ethernet

Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.

Hashing algorithm for network receive filtering

Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

DMA descriptor queue read and cache write pointer arrangement

An apparatus for edge enhancement of a digital image provided as raw digital image data to an input terminal and for providing processed image data to an output terminal. An offset processing circuit is coupled to the input terminal and configured to receive the raw data and generate offset data. An interpolation circuit is coupled to the offset processing circuit and configured to receive the offset data and to provide interpolated data. A color processing circuit is coupled to the interpolation circuit and configured to process the interpolated data to generate color data. An edge enhancement circuit is coupled to the interpolation circuit and the color processing circuit and configured to enhance the edges of the image based on the interpolated data and the color data to generate enhanced data. A lookup table is coupled to the color processing circuit and the edge enhancement circuit and configured to lookup the color data and the enhanced data to generate lookup data. A conversion circuit is coupled to the lookup table circuit and configured to convert the lookup data to generate the processed image data to the output terminal. In one aspect of the invention the processing is performed with RGB data, and in another aspect of the invention the processing is performed with YUV data. In another embodiment of the invention the edge enhancement circuit includes an edge extraction circuit, a cut-off level adjustment circuit and an edge gain scaling circuit. These circuits are used to define the edge of objects in the image and to enhance their respective edges. Advantages of the present invention include correctly locating object edges, and avoiding artifacts when the edges are enhanced. Consequently, the invention provides an improved image edge enhancement technique over conventional edge processors.

Method and apparatus for edge enhancement in digital images

A method and apparatus for providing audio in a digital video system. Equations for a value n are provided for replacement into the conventional audio data shuffling equations. The equations for the value n provide for simple, efficient techniques to, in turn, calculate values for track number (TK), block number (BK), and data position number (DP). The values TK, BK, DP can be used in an address generation scheme to generate a page value and an offset value. The page value and the offset value for a particular sample of digital audio data, in part, determine the location of the sample in a memory storing the digital audio data. The present invention can be implemented for both four channel and two channel modes under both the NTSC and the PAL standards in accordance with specifications set forth in the Digital Video Standard (the &ldquo;Blue Book&rdquo;).

Method and apparatus for providing audio in a digital video system

A translation-lookaside buffer includes a content-addressable memory (CAM) cell to generate a CAM current signal with a first transistor configuration having a set of transistors of a predetermined size and connection. A reference current circuit generates a reference current signal with a second transistor configuration corresponding to the first transistor configuration, with the exception of the size and connection of selected transistors. A match sense amplifier selectively generates a match signal in response to the CAM current signal and the reference current signal.

Translation-lookaside buffer with current tracking reference circuit

An image compression apparatus for compressing image data provided to an input terminal and providing compressed data to an output terminal includes a 4&times;4 weighted digital cosine transformer (DCT) coupled to the input terminal and configured to convert the image data into weighted frequency data. A zigzag circuit is coupled to the DCT and configured to zigzag process the frequency data and generate create zigzag data. A Q-factor estimator is coupled to the DCT and configured to estimate the frequency data and generate a Q-factor. A DC coding circuit is coupled to the zigzag circuit and configured to code the zigzag data and generate a DC code. A quantization circuit is coupled to the zigzag circuit and the Q-factor estimator and configured to quantize the zigzag data based on the Q-factor and generate quantized data. A run-length coding circuit coupled to the DC coding circuit and the quantization circuit and configured to encode the quantized data to create variable length data as the compressed data to the output terminal. In this manner, the original image is compressed. While the invention is described with reference to specific hardware, the invention can also be implemented in software employing the functions as described herein. Advantages of the present invention include an image compression technique that is both fast and efficient. Additionally, the invention provides a fast and efficient image compression technique that can be applied to moving images.

Method and apparatus for image compression

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San Jose, CA, United States of America

Der-Ren Chu