International Business Machines Corporation

Samsung Electronics Co., Ltd.

Deok-Kee Kim

Chandrasekharan Kothandaraman

Haining S Yang

Byeongju Park

William K Henson

Dureseti Chidambarrao

John Matthew Safran

Wai-Kin Li

Anil Kumar Chinthakindi

Ahmet Serkan Ozcan

Dennis Merton Newns

Bruce Gordon Elmegreen

Lia Krusin-Elbaum

Chung H Lam

Xiangdong Chen

Subramanian Srikanteswara Iyer

Kenneth Jay Stein

Oh-Jung Kwon

Dan Moy

Xi Li

Norman Whitelaw Robson

Seong-Dong Kim

Chih-Chao Yang

Lawrence Alfred Clevenger

Carl John Radens

Ramachandra Divakaruni

Keith Kwong Hon Wong

Sampath Purushothaman

Ping-Chuan Wang

Zhong-Xiang He

Douglas Duane Coolbaugh

Herbert Lei Ho

Robert Mark Rassel

Dae-Gyu Park

Roger Allen Booth, Jr

Ebenezer E Eshun

Hongwen Yan

Xiaojun Yu

Ephrem G Gebreselasie

Ho Jung Kim

Hoki Kim

Yongsang Cho

Byeung-Chul Kim

Hoon-Jeong

Yong-Woo Kwon

Kuang-Neng Chen

A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.

Semiconductor devices having E-fuse structures and methods of fabricating the same

An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

Structure and method to form e-fuse with enhanced current crowding

Structure and method to form E-fuse with enhanced current crowding

Semiconductor devices having e-fuse structures and methods of fabricating the same

A semiconductor device and an electronic system are provided. The semiconductor device includes a lower conductive pattern, and an intermediate conductive pattern on the lower conductive pattern. An upper conductive pattern is provided on the intermediate conductive pattern and is electrically connected to the intermediate conductive pattern. The intermediate conductive pattern includes a first portion and a second portion that extends from a part of the first portion and that is disposed at a higher level from the lower conductive pattern than the first portion. The upper conductive pattern is disposed on the first portion of the intermediate conductive pattern and has a top surface that is disposed at a higher level from the lower conductive pattern than the second portion of the intermediate conductive pattern.

Semiconductor devices and electronic systems

A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a feedback circuit for detecting a resistance change of the variable resistance device and controlling a gate voltage of the select transistor according to the detected resistance change.

Variable resistance memory device and related method of operation

Semiconductor device having e-fuse structure and method of fabricating the same

An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

Efuse containing sige stack

A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

Metal gate compatible electrical fuse

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor

An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link.

Structure and method to form dual silicide e-fuse

A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

Metal gate compatible electrical antifuse

eFuse containing SiGe stack

A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.

eFuse with partial SiGe layer and design structure therefor

A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

Electrical fuse having a fully silicided fuselink and enhanced flux divergence

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Bedford Hills, NY, United States of America

Deok-Kee Kim