Seoul National University

Skhynix Inc.

Silicon Image Gmbh

Gct Semiconductor, Inc.

Samsung Display Co., Ltd.

Sun Microsystems, Inc.

Samsung Electronics Co., Ltd.

Other

Deog-kyoon Jeong

Hynix Semiconductor Inc.

Goldstar Electron Co., Ltd.

Unidisplay Inc.

Snu Industry Foundation

Global Communication Technology Inc.

Deog-kyoon Jeog

Deog-Kyoon Jeong

Suhwan Kim

Kyeongho Lee

David D Lee

Yeshik Shin

Shing Kong

Yongsam Moon

Gijung Ahn

Moon-Sang Hwang

Mino Kim

Han-Gon Ko

Hyungrok Do

Gyudong Kim

Won-Jun Choe

Joo-Hyung Chae

Jiheon Park

Dongyun Lee

Hong Seok Choi

Han-Kyu Chi

Soyeong Shin

Joonbae Park

Sungjoon Kim

Youngmin Park

Kyo-Jin Choo

Bong-Joon Lee

Do-Hwan Oh

Jonghyun Oh

Jung Min Yoon

Sang-Hyun Lee

Wonchan Kim

Seok-Min Ye

Sang-Yoon Lee

Jaeha Kim

Woonghee Lee

Jaewook Kim

Moonsang Hwang

Chang-Ho Hyun

Kwangho Lee

Kyungyoul Min

Sungwoo Kim

Gi-Moon Hong

Jeongho Hwang

Hankyu Chi

Yongjae Lee

Young-Ha Hwang

Yunhee Lee

Jaewook Lee

Masashi Hashimoto

Ic-Su Oh

Taek-Sang Song

Sanghee Lee

Sang-hyun Lee

Hyojun Kim

Min-Kyu Kim

Sanghun Park

Min-Chang Kim

Ah-Reum Kim

Jong-Sang Choi

Weon-Jun Choe

Daejeong Kim

Byungjun Kang

Dong-Hyuk Lim

Tae Jun Ham

Hyunkyu Park

Woo-Yeol Shin

Jung Hun Park

Jinhyung Lee

Su-hwan Kim

Eunjoo Hwang

Younghwan Oh

Sungphil Choi

Minsoo Lim

KwangHoon Lee

Hyun-Chang Kim

Hee-Soo Song

Sung-Phil Choi

Won Jun Choe

Young Soo Park

Hyung-Rok Lee

JongSang Choi

Chan-Ho Kye

Hyeongjun Ko

So-Yeong Shin

Weon Jun Choe

Sungyong Cho

Seonghak Kim

Sungjun Jung

Joohyung Chae

Daeho Yun

Daehyun Koh

Moon-Chul Choi

Seungha Roh

Minkyo Shim

Dae-Hyun Koh

Woo-Rham Bae

Kwanseo Park

Sangjin Pak

Min-Seong Chu

A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.

Clock transfer circuit including a semiconductor device for compensating delay fluctuation

A receiver includes a sampling circuit configured to sample a comparison result between an input signal and a plurality of threshold voltages according to a sampling clock signal; a clock controller configured to generate the sampling clock signal according to a clock control signal; and a control circuit configure to generate the clock control signal and the plurality of threshold voltages according to a target value and an output of the sampling circuit. The control circuit operates to control a ratio of a magnitude of a main cursor of the input signal and a magnitude of a pre-cursor intersymbol interference to be the target value.

Receiver for removing intersymbol interference

A receiver includes an equalization circuit configured to output a data sample signal and an edge sample signal by sampling a data input signal according to clock signal, and to perform an equalization operation according to the data sample signal and the edge sample signal; and a clock gate circuit configured to select the clock signals from among a plurality of multi-phase clock signals according to a selection signal.

Receiver including a multi-rate equalizer

A semiconductor device includes a first switch coupling a first switch coupling a first power source and a first node according to a first control signal; a sense amplifier coupled between the first node and a second node and performing a sensing operation; a second switch coupling a second power source and the second node according to a second control signal; and a sense amplifier control circuit providing the first control signal and the second control signal. The sense amplifier control circuit controls the second control signal so that a voltage of the second node reaches a shift voltage higher than a voltage of the second power source during a first sensing period of the sensing operation and a bias current flows through the second node during a second sensing period of the sensing operation. The sensing period is subsequent to the first sensing period.

Semiconductor device including sense amplifier having enhanced sensing margin and method of controlling the same

A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

Receiver for receiving multilevel signal

A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.

Semiconductor device for compensating delay fluctuation and clock transfer circuit including the same

An accelerator includes a key matrix register configured to store a key matrix, a query vector register configured to store a query vector; and a preprocessor configured to calculate similarities between the query vector and the key matrix.

Method for candidate selection and accelerator for performing candidate selection

A display apparatus including a display panel, a touch sensing unit including first and second transmission touch lines, and a touch driving circuit to apply first and second touch driving signals to the first and second transmission touch lines, respectively, in which the touch driving circuit includes a first switch group including a first sharing switch device having one end connected to the first transmission touch line, and a second switch group including a second sharing switch device having two ends respectively connected to the second transmission touch line and another end of the first sharing switch device, and the touch driving circuit is configured to turn on the sharing switch devices during a first period such that the touch driving signals have a first voltage level, and turn on the sharing switch devices during a second period such that the touch driving signals have a second voltage level.

Display apparatus having touch driving circuit for generating driving signals for different levels

A driving circuit includes an input circuit slice configured to convert a data signal into a first data signal and a second data signal having different DC components. The driving circuit also includes a driver slice configured to output driving current at an output node by generating push current or pull current according to the first data signal and the second data signal, wherein a magnitude of the push current or the pull current is variable.

Driving circuit and an optical transmitter including the same

An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.

Integrated circuit and memory

A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source.

Phase-locked loop capable of compensating power noise

Provided is a transmitter performing at least feed-forward equalizing and crosstalk cancellation, the transmitter including: a main driver () generating waveform including data to be transmitted; and an FFE driver block () connected to the main driver in parallel, and generating waveform that is acquired by applying a sum of amplitude for feed-forward equalizing and amplitude for crosstalk cancellation, so as to adjust the waveform generated by the main driver.

Transmitter having merged FFE and XTC, and transmission method thereof

A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.

Semiconductor memory device including a control circuit for controlling a read operation

The present disclosure relates to an adaptation method for data level (dLev) or data swing detection in a high-speed link system for multi-level (e.g. PAM-4) signaling. Provided are a receiver and a receiving method in which when a swing range of data received as an input is changed according to a channel condition, reference levels of data/swing detection samplers are not adaptively controlled, but the reference levels are fixed and a variable gain amplifier (VGA) is adaptively controlled for response to the change. Through the present disclosure, offset calibration of the data/swing detection samplers is more accurately performed and lower bit error rate (BER) is thus achieved.

Method and apparatus for multi-level signaling adaptation with fixed reference levels

A clock and data recovery (CDR) device includes a data sampler configured to output a data signal by sampling an input signal according to a first clock signal; an edge sampler configured to output an edge signal by sampling the input signal according to a second clock signal, the second clock signal having substantially the same frequency as the first clock signal and having substantially an opposite phase to the first clock signal; an error detection circuit configured to identify a plurality of patterns based on the data signal and the edged signal and generate an error signal according to occurrence frequencies of the identified plurality of patterns; and an oscillation control circuit configured to generate a first oscillation control signal to control an oscillator generating the first and second clock signal according to the error signal.

Clock and data recovery device and training method thereof

Growing community of inventors

Seoul, South Korea

Deog-Kyoon Jeong