Sun Microsystems, Inc.

Extreme Networks, Inc.

Google Inc.

Denton Eugene Gentry, Jr

Rasoul Mirzazadeh Oskouy

David K Parker

Taliver Heath

Prakash Kashyap

Karl Robert Garcia

A system includes a power-consuming, at least one energy storage device, and a power management system. The facility is configured to receive electrical power from an electric utility grid. The energy storage device is located at the power consuming facility and is configured to store electrical energy from the electrical power received from the electric utility grid. The power management system is configured to receive, from the electric utility grid, a request that indicates an amount of power and, in response to the request, to cause at least a portion of the power-consuming facility to be powered by the at least one energy storage device rather than the power received from the electric utility grid such that an amount of the received power consumed by the power-consuming facility is reduced by at least the indicated amount.

Power-consuming facilities as a source of reserve power

A method of presenting different virtual routers to different end users, classes of service, or packets is provided. An incoming packet is received having a VLAN field and at least one additional field. A key is formed from the VLAN field and at least one other packet field, and mapped into a virtual router identifier (VRID) using an indirection mapping process. The VRID identifies a particular virtual router configuration from a plurality of possible virtual router configurations. A networking device is configured to have the particular virtual router configuration identified by the VRID, and the packet is then forwarded by the configured device.

Method of providing virtual router functionality

An Access Point receives an encrypted data frame from a client device, and determines whether the encrypted data frame is a guest frame. If it determined that the frame is a guest frame, the Access Point transmits the encrypted data frame to a server for decryption by the server, and determines whether to transmit an ACK to the client device based on the encrypted data frame. Otherwise, the Access Point decrypts the encrypted data frame, and determines whether to transmit an ACK to the client device.

Method, manufacture, and apparatus for centralized wifi encryption for guest

A system includes a power-consuming, at least one energy storage device, and a power management system. The facility is configured to receive electrical power from an electric utility grid. The energy storage device is located at the power consuming facility and is configured to store electrical energy from the electrical power received from the electric utility grid. The power management system is configured to receive, from the electric utility grid, a request that indicates an amount of power and, in response to the request, to cause at least a portion of the power-consuming facility to be powered by the at least one energy storage device rather than the power received from the electric utility to grid such that an amount of the received power consumed by the power-consuming facility is reduced by at least the indicated amount.

A MAC address detector for a networking device is provided, the device configured to present different virtual routers to different end users, classes of service or packets. First addressing logic provides a pool of N potential MAC addresses of the device, wherein N is an integer of one or more. Second addressing logic generates a (N+1)th potential MAC address of the device by combining a permanent or semi-permanent identifier of the device, for example, a chassis identifier, with a virtual router identifier determined responsive to the packet. Comparison logic indicates which if any of the (N+1) potential MAC addresses match the destination MAC address from the packet. Enable logic selectively activates responsive to the packet any of the (N+1) potential MAC addresses. Detection logic asserts a device address detection signal if any activated ones of the (N+1) potential MAC addresses match the destination address from the packet.

MAC address detection device for virtual routers

A method of providing virtual router functionality to a packet responsive to one or more abstracted virtual packet identifiers is provided. The method occurs in a networking device having a router core. The one or more abstracted virtual identifiers are abstracted from one or more virtual identifiers derived from the packet, thus insulating the router core from changes in the one or more virtual identifiers. A packet is received having a VLAN field, and a key is formed from the VLAN field and at least one other packet field. The key is mapped into an abstracted virtual identifier using an indirection mapping process. One or more core virtual router functions are then performed responsive to the abstracted virtual identifier.

Method of providing virtual router functionality through abstracted virtual identifiers

An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache. Top and bottom pointers are maintained, pointing to the most recently used and least recently used channels. When a channel is used, it moved to the top of the list. When channel data is moved from external memory to the cache, the bottom pointer points to the channel data to be removed from the cache.

Method and apparatus for multiple channel direct memory access control

A method and apparatus that provides for the atomic transfer of data associated with a command to be transferred to a device consisting of a cache memory which supports a plurality of virtual devices. The atomic transfer enables the device to initiate and complete execution of the command immediately with respect to a particular virtual device without having to wait for data to come during subsequent bus transfers. This insures that the state of the device will be consistent during execution of the command.

Method and apparatus for transmission and processing of virtual commands

A method and an apparatus for reducing data copying overhead associated with protected memory operating systems. In an ATM (Asynchronous Transfer Method) network, the present invention's NIC (network interface circuit) demultiplexes the information in the header of the incoming packet and routes the packet directly to its final destination using the present invention's concept of targeted buffer rings. Thus, instead of having the packet be DMA'd to a buffer in a descriptor ring in the kernel, it may be routed directly to the buffer ring of the destination process.

Mechanism for reducing data copying overhead in protected memory

A method and an apparatus for hardware and software interaction in data transfers of shared data structures in memory. The method and apparatus decreases the number of mutex lockings required to prevent conflict between different software attempting to access the same data and keeps the index value for each buffer in use in order to prevent conflicts between buffer replacement and packet arrival. In an exemplary implementation of the method and apparatus of the present invention, a receive hardware of a computer system keeps an index value for each buffer in use. This index value is placed in a completion ring protected by a mutex, and placed in a software queue protected by mutex. The mutexes assure that only one thread will possess a given index at a given time. No mutex locking is required for a buffer table containing software address and related information.

Method and apparatus for exclusive access to shared data structures

A method and apparatus of coordinating data transfer between hardware and software in a computer system through the use of a semaphore mechanism is disclosed. When a data packet is queued by preparing an entry in a data descriptor ring, software provides the descriptor entry number to a first storage field in a predetermined storage location which is accessible by hardware. Hardware accounts for the transactions it has completed by writing the descriptor entry number to a second storage field in the storage location. To determine if there is additional data to process, hardware compares the contents of the first storage field and the contents of the second storage field. If the contents of both storage fields are equal, the corresponding ring or channel has run out of data and no additional data is to be processed. Under this condition, the corresponding channel goes to sleep until it is waken by a command indicating that software has provided another descriptor entry number to the first storage field in the storage location. If the contents of both storage fields are not equal, hardware continues to process the data represented by the descriptors provided.

Method and apparatus for coordinating data transfer between hardware and

A circuit and method for generating a checksum for a TCP packet on the fly. A stream of 32-bit data words from a TCP packet is split into two 16-bit data word streams and separately summed using 16-bit adders. The carry-out from the adders is tied to the carry-in thereof so as to incorporate any carry bits generated into the sum. At the end of the data stream, three further summing cycles are used in order to generate the final 16-bit one's complement checksum. First, the two 16-bit data stream partial sums are added together, including any carry bit from one of the adders while the carry-out from the other adder is stored. In the second cycle the stored carry-out and the carry-out from the first cycle are added into the sum. In the third cycle, any carry bit generated in the second cycle is added to the sum so as to produce the final checksum.

Checksum generation circuit and method

Interrupts are presented to a processor to indicate the arrival of data packets from a high speed network. The rate of packet arrival interrupts is modulated to prevent burdening the processor unnecessarily with repeated interrupts while receiving a burst of data. The interrupt modulator of the present invention ensures that the first packet of a new data burst, or the first packet of a short message, generate an immediate interrupt to the processor, thus avoiding any unnecessary latency in the processor's response. This is done by enabling a packet arrival to generate an interrupt if a specified period of time has elapsed since the previous interrupt. Further, the interrupt modulator ensures that every N'th packet that arrives generates an interrupt--for example, to ensure that the processor performs any memory management functions that may be required. A packet does not generate an interrupt if it arrives soon enough after the previous interrupt and it is not the N'th packet since the pervious interrupt. This lowers the interrupt rate due to the arrival of a burst of data, thus enhancing processor and system performance.

Growing community of inventors

Fremont, CA, United States of America

Denton Eugene Gentry, Jr