Racyics Gmbh

Dennis Walter

Sebastian Höppner

Holger Eisenreich

A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

Method for characterization of standard cells with adaptive body biasing

A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance cof the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance cof the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

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Dresden, Germany

Dennis Walter