Johnstech International Corporation

Dennis Wagner

Jeffrey C Sherry

A system and method for reducing inductance and capacitance and shielding signals in an integrated circuit test for devices under test (DUT) is disclosed. Inductance and capacitance are reduced in two ways. First, by recessing the contact pin housingdirectly into the load boardthereby eliminating much of distance between the load board and DUT. Second, surrounding the slot/wellin which each RF contact pin resides in the housing with a ground isolation cageof electrically conductive strips or rings at the top and bottom of the housing adjacent the slot with connecting vias thereby creating an isolation cage against RF cross talk transmission and further lowering inductance and capacitance.

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Minneapolis, MN, United States of America

Dennis Wagner