International Business Machines Corporation

Dennis W Wittig

Ali Y Duale

Shailesh Ratilal Gami

Theodore Joseph Bohizic

John L Weber

Mark H Decker

Sandhya Venugopala

Mohammed Shammas

Vincent L Ip

Compare points are detected in a multi-threaded computing environment. One thread of the multi-threaded computing environment has reached a compare point for the one thread. The compare point for the one thread being a point at which results of executing a test case on the one thread is ready to be compared against expected results for that test case. A determination is made as to whether another thread of the multi-threaded computing environment has reached a compare point for the another thread. Execution of the another thread is continued, based on determining the another thread has not reached the compare point for the another thread. The test case of the one thread is, however, not re-executed.

Compare point detection in multi-threaded computing environments

Embodiments of the present invention are directed to a computer-implemented method for building and executing test cases. A non-limiting example of the computer-implemented method includes building, using a processor, a master test case instruction stream including a plurality of instructions including a replaceable instruction. The computer-implemented method builds, using the processor, a test case instruction stream derivative including the plurality of instructions including a replacement instruction in lieu of the replaceable instruction, and predicts, using the processor, a predicted result of executing the test case instruction stream derivative in a test case environment. The computer-implemented method executes, using the processor, the test case instruction stream derivative on the test case environment to generate an actual test case result and compares, using the processor, the actual test case result with the predicted result to determine proper operation of the test case environment.

Reduction of pseudo-random test case generation overhead

A validation and testing method is provided. The validation and testing method is executable by a processor coupled to a memory. The validation and testing method includes inserting intermediary save points within an instruction stream. The method includes executing the instruction stream including the intermediary save points. The method includes executing a save operation for data in one or more registers at each of the one or more intermediary save points.

Flexible and in-line register comparison for bug analysis

A testing facility is provided to test the multithreading functionality of a computing environment. The testing of this functionality includes building independent instruction streams to test threads of a multi-threaded environment while honoring architecturally imposed common fields and constraints, if any, of the threads. Certain features may be enabled/disabled for all threads. The instruction streams generated for testing this functionality may vary from being identical for all the threads being tested to being totally different, such as having different architectures.

System level testing of multi-threading functionality including building independent instruction streams while honoring architecturally imposed common fields and constraints

A computer-implemented method includes executing one or more tests on a computing device. The computing device has Instruction Execution Protection (IEP), and each test of the one or more tests includes selectively setting one or more IEP bits of one or more page tables, where each IEP bit prevents code in a respective storage block from being executed. During the one or more tests, an IEP exception is detected, by a computer processor, each time an attempt is made to execute code in a storage block for which a respective IEP bit is set. Test results of the one or more tests are determined based on the detecting. A remedial action is performed in response to the test results of the one or more tests.

Verifying proper operation of the instruction execution protection architecture

A computer-implemented method includes executing one or more test programs on a computing device, where the computing device includes a Guarded Storage (GS) facility managing use of GS. Each test program of the one or more test programs comprises a respective GS event, and each respective GS event prompts execution of a respective garbage reclaim function associated with the GS. A memory storage is analyzed, by a computer processor, to verify expected operation of each of the one or more test programs. Test results of the one or more test programs are determined based on the analyzing the memory storage. A remedial action is performed in response to the test results of the one or more test programs.

Testing a guarded storage facility

A computer-implemented method for testing a hybrid architecture instruction set is provided. The method includes defining a first instruction definition table for a first base architecture, and defining a second instruction definition table for a second base architecture, wherein the first base architecture is different than the second base architecture. The method also includes defining a delta table, wherein the delta table defines architecture specific behavior, and generating a hybrid architecture table based on the delta table and at least one of the first instruction definition table or the second instruction definition table. The method includes executing a test based on the hybrid architecture table, wherein the hybrid architecture table is for a hybrid architecture that is compatible between the first base architecture and the second base architecture.

Testing hybrid instruction architecture

An aspect includes include selective purging of entries from translation look-aside buffers (TLBs). A method includes building multiple logical systems in a computing environment, the multiple logical systems including at least two level-two guests. TLB entries are created in a TLB for the level-two guests by executing fetch and store instructions. A subset of the TLB entries is purged in response to a selective TLB purge instruction, the subset including TLB entries created for a first one of the level-two guests. Subsequent to the purging, verifying that the subset of the TLB entries were purged from the TLB, and determining whether a second one of the level-two guests is operational, the determining including executing at least one instruction that accesses a TLB entry of the second one of the level-two guests. Test results are generated based on the verifying and the determining. The test results are output.

Verifying selective purging of entries from translation look-aside buffers

An aspect includes receiving a symbol translation table (STT) that includes input symbols and their corresponding codewords. An entropy encoding descriptor (EED) that specifies how many of the codewords have each of the different lengths is also received. Contents of one or both of the STT and the EED are modified to generate a test case and an entropy encoding test is executed. The executing includes performing a lossless data compression process based on contents of an input data string that includes one or more of the input symbols, and on contents of the STT and the EED; or performing a data expansion process based on contents of an input data string that includes one or more of the codewords, and on contents of the STT and the EED. A result of the entropy encoding test is compared to an expected result.

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New Paltz, NY, United States of America

Dennis W Wittig