Intel Corporation

Dennis W Brzezinski

Pete D Vogt

Warren Morrow

Kuljit Singh Bains

Rajat Agarwal

John B Halbert

David Zimmerman

Kai Cheng

Michael W Williams

James W Alexander

Suresh S Chittor

Robert G Blankenship

Ioannis T Schoinas

Naveen Cherukuri

Akhilesh Kumar

Anahita Shayesteh

Mani Azimi

Henk G Neefs

Edwin F Mendez Valverde

Scott Huddleston

A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.

Method and system for error management in a memory device

In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.

Replacing cache lines in a cache memory based at least in part on cache coherency state information

Described herein are 8-bit wide data error detection and correction mechanisms that require fewer memory chips and therefore provide reduces system complexity and reduced system power consumption as compared to traditional mechanisms. This technique relies on testing a fixed set of possible solutions in order to correct the fault. This error code provides a very high error detection rate, but requires a set of error trials to correct the detected faults. The extra correction latency for infrequent errors may be acceptable given a low frequency. For repeated corrections, a log may be maintained to simplify error correction.

Error correction mechanisms for 8-bit memory devices

Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Disabling outbound drivers for a last memory buffer on a memory channel

In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.

Poison bit error checking code scheme

An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error.

Memory error detection and/or correction

Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame.

Systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code

Memory channel with bit lane fail-over

Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

Mitigating silent data corruption in a buffered memory module architecture

Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

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Sunnyvale, CA, United States of America

Dennis W Brzezinski