University of Michigan

Arm Limited

University of California

Dennis Sylvester

David Theodore Blaauw

Trevor N Mudge

David Alan Fick

Sudhir Kumar Satpathy

Gregory Kengho Chen

Scott McLean Hanson

Yoonmyung Lee

Puneet Gupta

Andrew B Kahng

Sechang Oh

Taekwang Jang

Bharan Giridhar

Jie Yang

Michael B Henry

Krisztian Flautner

Himanshu Kaul

Hun-Seok Kim

Todd Austin

Qing Dong

Ronald George Dreslinski, Jr

Wanyeong Jung

Yejoong Kim

Kyojin Choo

Matthew Rudolph Fojtik

Seok Hyeon Jeong

Myungjoon Choi

Stuart David Biles

Brian Tracy Cline

Jae-Yoon Sim

Li Xu

Skylar Skrzyniarz

Laura E Fick

Massimo Alioto

Cynthia Anne Chestek

Paras Patel

In Hee Lee

Michael John Wieckowski

Kaiyuan Yang

Li-Xuan Chuo

Mohammad Hassan Ghaed

Nurrachman Chih Yeh Liu

Zhiyoong Foo

Nathaniel Pinckney

Gyouho Kim

Mingoo Seok

Suyoung Bang

Yimai Peng

David Kyojin Choo

Rohit Rothe

Jamie Phillips

Jongyup Lim

Eunseong Moon

Julianna Richie

Michael Barrow

Mingyu Yang

Samuel Nason

Ronald G Dreslinski

Yen-po Chen

Inhee Lee

A motion sensing system uses high-voltage biasing to achieve high resolution with ultra-low power. The motion sensing system consists of a motion sensor, a readout circuit, and a high-voltage bias circuit to generate the optimized bias voltage for the motion sensor. By using the high-voltage bias, the signal from the motion sensor is raised above the readout circuit's noise floor, eliminating the power-hungry amplifier and signal-chopping used in conventional motion sensing systems. The bias circuit, while producing the programmable bias voltages for the motion sensor, also compensates for the process mismatch raised by the high voltage biases.

Ultra-low power readout circuit with high-voltage bias generation for MEMS accelerometer

A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Wireless neural recording devices and system with two stage RF and NIR power delivery and programming

An amplifier is presented with a sample and average common mode feedback resistor. The amplifier circuit includes a feedback capacitor and a feedback resistor in parallel with the feedback capacitor, where the feedback capacitor and the feedback resistor form part of the negative feedback path for the amplifier. Of note, the feedback resistor is comprised of a low pass filter in series with a switched capacitor resistor, such that the low pass filter is electrically coupled to the output of the amplifier circuit and the switched capacitor resistor is electrically coupled to the inverting input of the amplifier circuit. The amplifier circuit further includes a control circuit interfaced with switches of the switched capacitor resistor. The high pass corner of the switched capacitor resistor is preferably lower than corner of the low pass filter.

Amplifier with sample and average common mode feedback resistor

A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices.

Low-power, long-range RF localization system and method

An analog-to-digital converter (ADC) circuit is present, which is particularly suitable for use in an image sensor. The ADC circuit includes a comparator and a digital-to-analog converter (DAC) circuit. The DAC circuit includes two or more charge paths electrically coupled to the output node. Each charge path is formed by one or more charge-injection cells electrically coupled via a gain capacitor to the output node, and a charge conversion capacitor electrically coupled in parallel with the one or more charge-injection cells. Each charge-injection cell is configured to transfer a fixed amount of charge from a charge source to an associated charge path and includes at least one switch configured to isolate the charge source from the output node.

Analog-to-digital conversion circuit and image sensor including the same

A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer &#x3c3;/&#x3bc; of 0.26% and wafer-to-wafer &#x3c3;/&#x3bc; of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/&#xb0; C. from &#x2212;40&#xb0; C. to 85&#xb0; C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25&#xb0; C.

Variation-tolerant voltage reference

An intraocular pressure sensor is presented that achieve very low power consumption. The intraocular pressure sensor takes the form of an implantable assembly configured to be implanted in an eye of a subject. Specifically, the implantable assembly is comprised of a capsular tension ring attached to a flexible printed circuit board. The flexible printed circuit board includes a cutout that is sized to encircle the pupil of the eye and is C shaped. One or more electrical components are also mounted onto the flexible printed circuit board. One such component is a voltage reference generator that is implemented by a circuit which provides inherently low process variation and low power consumption.

Intraocular pressure sensor with improved voltage reference circuit

An environmental sensor implementing a sleep mode timer with an oscillator circuit suitable for low power applications is presented. The oscillator circuit includes a plurality of timer stages cascaded in series with each other. Each timer circuit includes a plurality of transistors and operates to output two voltages with opposite polarities, such that the polarities of the two voltages oscillate periodically based on leakage current in the plurality of transistors. Each timer circuit further includes one or more tuning transistors that operate to adjust a frequency at which the polarities of the voltages oscillate. A complementary-to-absolute temperature ('CTAT') voltage generator is configured to receive a regulated voltage and supply a bias voltage to the one or more tuning transistors in each of the plurality of timer circuits, where the CTAT voltage generator adjusts the bias voltage linearly and inversely with changes in temperature.

Environmental sensor

A self-oscillating DC-DC converter structure is proposed in which an oscillator is completely internalized within the switched-capacitor network. This eliminates power overhead of clock generation and level shifting and enables higher efficiency at lower power levels. Voltage doublers are cascaded to form a complete energy harvester with a wide load range from 5 nW to 5 &#x3bc;W and self-starting operation down to 140 mV. Because each doubler is self-oscillating, the frequency of each stage can be independently modulated, thereby optimizing the overall conversion efficiency.

Self-oscillating switched-capacitor DC-DC converter

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.

Floating-gate transistor array for performing weighted sum computation

An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

Electrostatic discharge clamp circuit for ultra-low power applications

A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period. A reference ring oscillator has a plurality of reference unit cells arranged to form a reference ring, and generates a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period. Calculation circuitry then determines the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period. This provides a particularly simple and accurate mechanism for calculating the clock node to output node delay of a flip-flop.

Measurement circuitry and method for measuring a clock node to output node delay of a flip-flop

A temperature insensitive sub-nA current reference is presented with pA-range power overhead. The main concept is to linearly reduce the gate voltage of a sub-threshold-biased MOSFET as temperature increases, in order to compensate for exponential dependence of drain current on temperature. For example, a MOSFET-only, 20 pA, 780 ppm/&#xb0; C. current reference that consumes 23 pW is disclosed, marking the lowest reported power among current references. The circuit exploits sub-threshold-biased MOSFETs and a complementary-to-absolute temperature (CTAT) gate voltage to compensate for temperature dependency. The design shows high immunity to supply voltage of 0.58%/V and a load sensitivity of 0.25%/V.

Ultra low power temperature insensitive current source with line and load regulation

A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased.

Protocol for an electronic device to receive a data packet from an external device

Synchronisation circuitrycomprises a first dynamic circuit stagegenerating a first stage state signal which is pulse amplified by pulse amplifying circuitryto generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stagewhere it is used to control generation of a second stage state signal. The pulse amplifying circuitrycomprises a chain of serially connected skewed invertersThe action of the pulse amplifying circuitryis to reduce the probability of metastability in the output of the second dynamic stage

Dynamic circuitry using pulse amplification to reduce metastability

Growing community of inventors

Ann Arbor, MI, United States of America

Dennis Sylvester