Taiwan Semiconductor Manufacturing Comp. Ltd.

Marvell International Limited

Mosys, Inc.

International Business Machines Corporation

Marvellworld Trade Ltd.

Dennis Sinitsky

Tao Shui

Chen-Jong Wang

Kuo-Chyuan Tzeng

Wingyu Leung

Shafiq M Jamal

Gang-feng Fang

Junshi Qiao

Ramachandra Divakaruni

Subramanian Srikanteswara Iyer

Bomy A Chen

Wen-Chuan Chiang

Paul David Agnello

Scott W Crowder

Ming-Hsiang Chiang

Fu-Chieh Hsu

Pei Wang

Song Chen

Haiqing Zhang

Wen-Chaun Chiang

A resonant element driver circuit includes a NMOS transistor and a PMOS transistor that are configured to drive a resonant element. The resonant element driver circuit includes biasing circuitry that is configured to bias the PMOS transistor. The biasing circuitry receives a reference signal that is used to set the biasing on the PMOS transistor. The resonant element driver further includes mirror circuitry that tracks current flowing through the NMOS and PMOS transistors.

Class-AB XTAL circuit

New and highly stable oscillators are disclosed. Such an oscillator may include a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator.

Precision oscillator with temperature compensation

Aspects of the disclosure provide a circuit. The circuit includes a signal amplifying circuit coupled with a crystal component of a natural frequency to form a crystal oscillator, and a signal generator circuit configured to generate a signal with an energy distribution about the natural frequency, and to provide the signal to the crystal oscillator to assist the crystal oscillator to begin oscillating.

Method and apparatus for starting up oscillation

An oscillator includes a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator.

In one embodiment, the present invention includes a circuit for suppressing noise with adaptive charge-pump regulation. The circuit comprises an oscillator circuit, a charge pump, an amplifier, a current mirror, and a filter. The charge-pump receives an oscillating signal and provides an output voltage. The amplifier is responsive to the output voltage and a reference voltage and provides a control signal. The control signal alters a frequency of the oscillator and the output voltage is responsive to this frequency. The current mirror and filter suppress a noise component of the output voltage. The current mirror provides a supply current to a regulator loop. The regulator loop is operable to generate a consistent regulator voltage. In this manner, the adaptive charge-pump allows for a more consistent, noise free, regulator voltage.

Circuit and methods of adaptive charge-pump regulation

A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process

A start-up circuit for a bandgap reference circuit includes a sampling circuit for sampling current through a diode in one of first and second diode/resistor networks that respectively provide complementary PTAT and CTAT characteristics in the bandgap reference, and a current injection circuit to inject current to a PMOS bus of the bandgap reference if the sampled current is not higher than a pre-designated low value. By virtue of this operation, since current through the diode itself is sampled, the start-up circuit ensures that current through the sampled diode is higher than the pre-designated low value, thereby leading to rapid start-up of the bandgap reference to a stable operating point.

Start-up circuit for bandgap reference

A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

Non-volatile memory in CMOS logic process

A non-volatile memory (NVM) cell fabricated on a semiconductor substrate, and including a floating gate electrode (which extends at least partially over all active regions of the NVM cell). The NVM cell also includes a PMOS access transistor located in a first n-type region, a PMOS control capacitor located in a second n-type region (separate from the first n-type region), and an NMOS programming transistor located in a p-type region. The floating gate electrode is a continuous electrode which extends over the active regions of the PMOS access transistor, the PMOS control capacitor and the NMOS programming transistor. Various array connections are provided for implementing arrays using this NVM cell. The PMOS access transistor and NMOS programming transistor can be replaced with an NMOS access transistor and a PMOS erase transistor, respectively, in an alternate embodiment.

Non-volatile memory in CMOS logic process and method of operation thereof

An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.

Fabrication process for increased capacitance in an embedded DRAM memory

A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.

Embedded dual-port DRAM process

A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Semiconductor chip having both compact memory and high performance logic

A random access memory cell and a method for fabrication thereof provide a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate. Within the random access memory cell and method: (1) a single fluorinated silicon oxide layer of a single thickness serves as both a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the metal oxide semiconductor capacitor device; and (2) a channel region within the field effect transistor device has a different threshold voltage adjusting dopant concentration in comparison with a semiconductor plate region within the metal oxide semiconductor capacitor device. The random access memory cell is fabricated with enhanced performance.

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Sunnyvale, CA, United States of America

Dennis Sinitsky