Intel Corporation

Apple Inc.

Intel Corporatoin

Dennis Ryan Bradford

Edward Thomas Grochowski

Robert Valentine

Mark Jay Charney

Jesus Corbal

Thomas D Fletcher

Milind Baburao Girkar

Andrew Thomas Forsyth

Jonathan Cannon Hall

Kent D Glossop

Brian J Hickmann

Jesus Corbal San Adrian

Lisa K Wu

Elmoustapha Ould-Ahmed-Vall

Bret L Toll

Robert Dale Cavin

Paul Caprioli

Suleyman Sair

Seth Abraham

Charles R Yount

Sridhar Samudrala

Jeffrey G Wiedemeier

James Charles Abel

Warren E Ferguson

Roger Espasa Sans

Santiago Galan Duran

Gilbert A Neiger

Rajesh M Sankaran

Eriko Nurvitadhi

Koichi Yamada

Joseph Nuzman

Deborah T Marr

Stephen R Van Doren

Lokpraveen B Mosur

Narayan Ranganathan

Jonathan D Pearce

Niall D McDonnell

Richard J Greco

Ganesh Venkatesh

Jeffrey J Cook

Asit K Mishra

Dwight P Manley

David B Sheffield

Tracy Garrett Drysdale

Nicholas P Carter

Roman S Dubtsov

Michael A O'Hanlon

Nikita A Shustrov

Rohan Sharma

Simon C Steely, Jr

Barry Tannenbaum

Linda J Rankin

Kermin Elliott Fleming, Jr

Roger Gramunt

Nagabhushan Chitlur

Fabrizio Petrini

Benjamin Keen

Mitchell Diamond

Yongzhi Zhang

Taraneh Bahrami

Paul M Stillwell, Jr

Amit Gradstein

Wei Wu

George Zacharias Chrysos

Brian S Morris

Bernard Joseph Semeria

Jonathan M Eastep

Michael D Upton

Brett Stanley Feero

Richard F Russo

Gaurav Garg

James Vash

Federico Ardanaz

Benjamin C Chaffin

Dror Markovich

Jeff Gonion

Kermin ChoFleming

Chinmay Ashok

Andrew Yang

Michael Rotzin

Krishnakumar Nair

Mark Charney

Maciej Urbanski

Thomas B Maciukenas

Jesus San Adrian Corbal

Jingwei Zhang

Michael Ferry

Avi A Tevet

Robert N Hanek

Louise Huot

Robert C Valentine

Niall D Mcdonnell

Michael A O'HANLON

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Remote cache invalidation

Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a corresponding product, shift the corresponding products with a set of shift registers based on a maximum exponent of exponents for the corresponding products determined by a maximum exponent determiner to produce shifted products, perform an numeric conversion operation on the shifted products with a set of numeric conversion circuits based on sign bits from the same element position of the first floating-point vector and the second floating-point vector to produce signed representations of the shifted products, add the signed representations of the shifted products with a set of adders to produce a single product, and normalize the single product with a normalization circuit based on the maximum exponent into a single floating-point resultant, and in the second mode, each multiplier of the set of multipliers is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product with the set of adders to produce a single integer resultant.

Apparatuses and methods to accelerate matrix multiplication

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

Embodiments of systems, apparatuses, and methods for chained fused multiply add. In some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. A register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. Execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.

Systems, apparatuses, and methods for chained fused multiply add

Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.

Apparatuses, methods, and systems for operations in a configurable spatial accelerator

Systems, methods, and apparatuses relating to swizzle operations and disable operations in a configurable spatial accelerator (CSA) are described. Certain embodiments herein provide for an encoding system for a specific set of swizzle primitives across a plurality of packed data elements in a CSA. In one embodiment, a CSA includes a plurality of processing elements, a circuit switched interconnect network between the plurality of processing elements, and a configuration register within each processing element to store a configuration value having a first portion that, when set to a first value that indicates a first mode, causes the processing element to pass an input value to operation circuitry of the processing element without modifying the input value, and, when set to a second value that indicates a second mode, causes the processing element to perform a swizzle operation on the input value to form a swizzled input value before sending the swizzled input value to the operation circuitry of the processing element, and a second portion that causes the processing element to perform an operation indicated by the second portion the configuration value on the input value in the first mode and the swizzled input value in the second mode with the operation circuitry.

Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator

Growing community of inventors

Portland, OR, United States of America

Dennis Ryan Bradford