Cypress Semiconductor Corporation

Monterey Research, LLC

Dennis Raymond Seguine

Harold Kutz

Eashwar Thiagarajan

Mark E Hastings

Warren S Snyder

Monte F Mar

Bert Sullam

Bruce E Byrkett

Timothy John Williams

James H Shutt

Gajender Rohilla

David Gordon Wright

Nathan Wayne Kohagen

Hans Klein

Jaskarn Singh Johal

Kendall V Castor-Perry

Paul M Walsh

Louis W Bokma

Ata Khan

Daniel O'Keeffe

Carl Liepold

Jean-Paul Vanitegem

Kofi Makinwa

Andrew C Page

Amsby D Richardson, Jr

Onur Ozbek

Anasuya Pai Maroor

Çagri Gürleyük

Erhan Hancioglu

Warren S Synder

Dermot MacSweeney

Matheus Pimenta

Hans Van Antwerpen

Douglas H Anderson

Gaurang Kavaiya

Jon Keith Perrin

Archana Yarlagadda

Derek Richardson

Adriy Ivanets

Kendall Castor-perry

Dermot Macsweeney

Amsby Richardson

Jaskam Singh Johal

Front-end circuits that combine inductive and capacitive sensing are described. In one embodiment, an apparatus includes a plurality of inductive elements, an inductive measurement circuit, and a frequency divider circuit. The inductive measurement circuit is to output a first signal with a first frequency. The first signal is associated with an inductance change of one of the inductive elements. A feedback circuit can maintain the sinusoidal operation of the first signal. The frequency divider circuit can generate a second signal with a second frequency that is lower than the first frequency.

High performance inductive sensing all digital phase locked loop

One inductive sensor is configured to maintain a fixed frequency in a resonant circuit. One apparatus includes an inductance-to-digital converter (LDC). The LDC includes a digital filter to measure an inductance change of a sensor and convert the inductance change to a digital value. The LDC further includes a digital control loop to maintain a fixed frequency in the sensor. The sensor forms an oscillator in the digital control loop. An output of the digital control loop is representative of the inductance change of the sensor.

One embodiment includes and I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.

Input/output multiplexer bus

A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

Combined analog architecture and functionality in a mixed-signal array

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Programmable switched capacitor block

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

Integrated circuit device with programmable analog subsystem

A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

A first portion of a programmable switched capacitor block includes a first plurality of switched capacitors and a second portion of the programmable switched capacitor block includes a second plurality of switched capacitors. A first switch associated with the first plurality of switched capacitors as well as a second switch associated with the second plurality of switched capacitors may be configured based on a type of analog function that is to be provided. The configuring of the first analog and the second analog block may include the configuring of the first switch associated with the first plurality of switched capacitors when the analog function operates on a first single ended signal and the configuring of both the first and second switches when the analog function operates on a differential signal.

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

One embodiment includes an I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.

Growing community of inventors

Temecula, CA, United States of America

Dennis Raymond Seguine