Delco Electronics Corporation

Delphi Technologies, Inc.

Other

Delco Electronics Corporaiton

Delco Electronics Corpooration

Dennis Michael Koglin

Mark Billings Kearney

Hamid Reza Borzabadi

Robert Harrison Reed

Stephen P Long

Douglas Bruce Osborn

Gregory J Manlove

Timothy A Vas

Ronald E Brown

John M Hart, Jr

William P Whitlock

Michael J Luettgen

Jeffrey A Michael

The present invention relates to a circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage. First, second and third capacitors are used, the first and second capacitors being matched, the third capacitor serving as an accumulator. A first switch is coupled to one end of the first capacitor, and a second switch is coupled between the one end of the first capacitor and one end of the second capacitor. A third switch coupled between the one end of the second capacitor and one end of the third capacitor, with a discharge circuit being coupled between the one end of the third capacitor and an opposite end of the second capacitor. When the third switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor. The third switch is closed when the analog input voltage is greater than a reference voltage, and wherein the first switch is closed to discharge the first capacitor followed by opening the first switch and closing the second switch to cause charge on the second capacitor to divide equally between the first and second capacitors when the analog input voltage is not greater than the reference voltage. Logic circuitry may also control the conversion according to a clock pulse.

Matched charge exchange circuit for analog and digital conversion

The present invention relates to a circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage. First, second and third capacitors are used, the first and second capacitors being matched, the third capacitor serving as an accumulator. A first switch is coupled to one end of the first capacitor, and a second switch is coupled between the one end of the first capacitor and one end of the second capacitor. A third switch coupled between the one end of the second capacitor and one end of the third capacitor, with a discharge circuit being coupled between the one end of the third capacitor and an opposite end of the second capacitor. When the third switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor. The third switch is closed when the analog input voltage is greater than a reference voltage, and wherein the first switch is closed to discharge the first capacitor followed by opening the first switch and closing the second switch to cause charge on the second capacitor to divide equally between the first and second capacitors when the analog input voltage is not greater than the reference voltage.

A leak-testing technique and apparatus for differential pressure sensor arrays is provided. A reference pressure sensor array is provided, wherein a seal is disposed between the reference pressure sensor array and a target differential pressure sensor array. A probe socket is utilized to communicate with each individual sensor in the reference pressure sensor array. The target pressure sensor array and the reference pressure sensor array are sealed via a pressure plate and plunger assembly. The target pressure sensor array, seal, and reference pressure sensor array are exposed to a first pressure. The target differential pressure sensor array, seal, and reference pressure sensor array are then exposed to a second pressure. The probe socket verifies that all reference pressure sensors continue to output the first pressure. If the probe socket identifies a reference pressure sensor that reads the second pressure, then the corresponding target pressure sensor is identified as being defective because of leakage.

Leak-testing technique for differential pressure sensor array

A technique for manufacturing an integrated pressure sensor includes a number of steps. Initially, a substrate with conductive electrical traces located on first and second sides of the substrate is provided. A plurality of compensation circuits are positioned in an array on the first side of the substrate in electrical contact with one or more of the conductive electrical traces on the first side of the substrate. A plurality of pressure sensors are positioned on the second side of the substrate in electrical contact with one or more of the conductive electrical traces on the second side of the substrate. Each one of the sensors is associated with one of the compensation circuits to form a plurality of pressure sensor-compensation circuit pairs. The substrate includes conductive vias to electrically connect each of the sensor-compensation circuit pairs. Each of the compensation circuits provides temperature compensation for an associated one of the sensors. The sensor-compensation circuit pairs are calibrated and singulated for final packaging.

Integrated pressure sensor and method of manufacture

A pressure sensor module is provided with an isolation platform which isolates stress. The pressure sensor module includes a base structure and a cantilever member formed in the base structure by an isolation gap. A pressure sensing element is located on the cantilever member such that the cantilever member provides stress isolation to the pressure sensing element.

Pressure sensor module having stress isolation platform

A multiplier and corresponding method are provided for amplifying a voltage difference between a first input voltage and a second input voltage, the multiplier being implemented with Bipolar Junction Transistor technology having high emitter resistance. The multiplier includes a first bipolar input transistor having high emitter resistance that receives the first input voltage and a second bipolar input transistor having high emitter resistance that receives the second input voltage. The multiplier also includes a first current source for generating a first current that flows through said first bipolar input transistor, a current mirror for producing a second current that is substantially equal to said first current and flows through said second bipolar input transistor. A range select impedance forms a first voltage loop with said first bipolar input transistor and said second bipolar input transistor and translates the voltage difference between the first input voltage and the second input voltage into a differential current. The differential current varies said second current and alters a base-to-emitter voltage of said second bipolar input transistor. A second voltage loop is provided that includes said second bipolar input transistor, the second voltage loop providing a relationship between said base-to-emitter voltage of said second bipolar input transistor and a multiplier current that represents the difference between the first input voltage and the second input voltage.

Integrated differential voltage amplifier with programmable gain and

A supply and temperature dependent linear signal generating circuit includes four transistors each having a unique current flowing therethrough and connected together to form a current multiplier. A first one of the currents is designed to be supply dependent and preferably adjustable in magnitude, a second one is designed to exhibit a specific temperature dependence, the third is designed to be both supply and temperature independent and the fourth current is defined as a ratio of the first three. The fourth current is, in one embodiment, impressed upon a network defined by a resistor divider and a voltage source to thereby define an output voltage V(T) that is both supply and temperature dependent according to the following equation:

Supply and temperature dependent linear signal generator

In accordance with the teachings of the present invention, a programmable integrated transducer amplifier circuit is provided which receives differential outputs from a transducer, such as a pressure or accelerometer transducer. The programmable integrated transducer amplifier circuit includes binary adjustable circuits that are programmed in response to binary coded signals. The binary adjustable circuits generate binary weighted currents that are employed to adjust the operating characteristics of the amplifier circuit. The binary coded signals are received from a programmable memory array which includes a plurality of memory cells that store binary information. Each of the memory cells are programmed when coupled to a programming signal. Additionally, the memory array has pretest capability for testing outputs of the memory cells prior to permanently programming the respective memory cells. Additionally, the integrated transducer amplifier circuit automatically compensates for variations in the operating temperature of the amplifier circuit. The method of temperature compensation is accomplished by operating the programmable integrated transducer amplifier circuit at a first temperature such that a temperature compensation voltage is 'nulled' or is forced to equal zero. Thereafter, the integrated transducer amplifier circuit is operated at other temperatures such that the temperature compensation voltage is generated in a manner representing the difference between the first operating temperatures and the current operating temperature.

Integrated transducer amplifier with zener-zap programming

A memory cell having programming voltage margin verification is provided. The memory cell includes a voltage comparator having a differential input with first and second inputs and bias circuitry for generating a differential input voltage. A voltage offset is applied to the second input of the comparator to provide an input offset voltage. A programming voltage is received for programming the memory cell and the memory cell provides an output signal. To verify an unprogrammed state voltage margin of the memory cell, a margin detection circuitry receives a verification check signal and the output is monitored to determine whether the unprogrammed state voltage margin is proper. To verify a proper programmed state voltage margin of the memory cell, current is sensed through the programming input and a determination of a proper programmed state voltage margin is determined as a function of the sensed current.

Memory cell having programmed margin verification

An analog voltage address decoder circuit and stackable voltage comparator circuit are provided. The address decoder circuit has a column decode comparator network made up of a first plurality of interconnected comparator circuits and a row decode comparator network made up of a second plurality of interconnected comparator circuits. The column decode comparator network compares a plurality of reference voltages with an analog input voltage so as to detect if the analog input voltage is within a bounded window. Likewise, the row decode comparator network compares an analog input voltage with a plurality of reference voltages to detect if the analog input voltage is within a bounded window. Detection within the proper bounded windows for the rows and columns produces a corresponding 'high' binary output to a particular memory location for access thereto. The decode comparator networks use stackable voltage comparator circuits to perform the voltage window comparisons. Each comparator circuit includes a differential input stage made up of a pair of transistors and receiving a current source. A current mirror is coupled to the differential input state. Successive comparator circuits are coupled together via interconnected input lines.

Analog voltage address decoder circuit

In accordance with the teachings of the present invention, a temperature dependent voltage generator circuit is provided for generating an output voltage that changes proportionally with changes in the operating temperature of the temperature dependent voltage generator circuit. The temperature dependent voltage generator circuit includes binary weighted current sources and electronic switches that are selectively closed in order to produce a binary weighted current. The binary weighted current is adjustable such that the output voltage of the temperature dependent voltage generator circuit may be 'nulled' or forced to zero at any given operating temperature.

Temperature dependent voltage generator with binary adjustable null

A 'zener-zap' memory cell with pretest capability for testing effects that would be realized from permanently programming the memory cell is provided. The memory cell is addressable and provides a binary signal at an output. The memory cell uses a zener diode as a memory element which is permanently programmed when selectively coupled to a programming voltage which exceeds the reverse breakdown voltage of the zener diode. The memory cell has a test circuit for generating the programmed binary signal at the output of the memory cell prior to permanently programming the zener diode and when coupled to a pretest voltage.

Integrated zener-zap nonvolatile memory cell with programming and

Programmable transducer amplifier circuit

A stackable voltage comparator circuit that may be used in an analog voltage address decoder circuit for performing voltage window comparisons. The voltage comparator circuit includes a plurality of voltage comparator circuit cells, each of which includes a differential input stage made up of a pair of transistors which receives a current source. A first comparator circuit cell includes a differential input pair of transistors with one of the transistors having a first collector and a second collector, with the second collector being coupled to an output line. The first comparator circuit cell compares an input window with a first threshold voltage and produces an output at the output line. A second comparator circuit cell compares the input voltage with a second threshold voltage and includes a second differential input pair of transistors. The second comparator circuit cell has an input coupled to the output line of the first comparator circuit for receiving current when the input voltage is less than the first threshold voltage and provides an output indicative of whether the input voltage is within a voltage window bounded by the first and second threshold voltages.

Stackable voltage comparator circuit for a multiple voltage window

An adjustable temperature dependent current generator includes a transconductance current multiplier, a current mirror, two temperature dependent current generating circuits and a current source to generate currents capable of having an adjustable linear relation to temperature.

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Carmel, IN, United States of America

Dennis Michael Koglin