International Business Machines Corporation

Egypt Nanotechnology Center

Other

Krusin-elbaum, Lia

Newns, Dennis M.

Dennis Merton Newns

Paul Michael Solomon

Chung H Lam

Seyoung Kim

Xiao Hu Liu

Kevin W Brew

Matthew R Wordeman

Kuan-Neng Chen

Sampath Purushothaman

Talia S Gershon

Teodor Krassimirov Todorov

Ramachandran Muralidhar

Xiao Lin Sun

Martin Michael Frank

Thomas M Shaw

Matthew Warren Copel

Effendi Leobandung

Ali Afzali-Ardakani

Alejandro Gabriel Schrott

Chandrasekharan Kothandaraman

Stephen Mark Rossnagel

Gustavo Alejandro Stolovitzky

Tayfun Gokmen

Yurii A Vlasov

Stefan Harrer

Stanislav Polonsky

Jing Li

Lawrence Alfred Clevenger

Subramanian Srikanteswara Iyer

Mark Alan Lavin

Pratap Chandra Pattnaik

Bipin Rajendran

Jonathan Zanhong Sun

Yasunao Katayama

Bruce Gordon Elmegreen

Glenn John Martyna

Lia Krusin-Elbaum

Jin-Ping Han

Binquan Luan

Jin Ping Han

Deok-Kee Kim

Yulong Li

Chang Chyi Tsuei

Albert M Young

Hongbo Peng

Xin Zhang

Robert L Sandstrom

James Patrick Doyle

Byeongju Park

Christy Sensenich Tyberg

Xiaodong Cui

Ahmed Maarouf

Ahmed Abou-Kandil

Wilm Ernst Donath

Marcelo A Kuroda

Hisham S Mohamed

Nader M Nassar

Gustavo Enrique Tellez

Grant Douglas Miller

Xinlin Wang

Daniel Nelson Maynard

Kirsten Emilie Moselund

Simone Raoux

Roger Hilsen Koch

Ralph Linsker

Saurabh Singh

Archibald John Allen

David P DiVincenzo

Roger D Traub

Alan Dziedzic

Rudolf Ludeke

Martin Muser

Kuang-Neng Chen

Jim Rozen

A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Area and power efficient implementation of resistive processing units using complementary metal oxide semiconductor technology

A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

Piezo-junction device

Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

Analog circuit for softmax function

A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

BEOL cross-bar array ferroelectric synapse units for domain wall movement

A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit

A controllable resistive element and method for updating the resistance of the same includes a state device configured to provide a voltage-controlled resistance responsive to a voltage input. A battery is configured to apply a voltage to the voltage input of the state device based on a charge stored in the battery. A write device is configured to charge the battery responsive to a write signal. An erase device is configured to discharge the battery responsive to an erase signal.

Battery-based neural network weights

A method for updating the resistance of a controllable resistance element includes determining an amount of resistance change for the controllable resistive element. A charge difference for a battery is determined corresponding to the resistance change for the controllable resistive element. The battery is charged or discharged to effect the resistance change in the controllable resistive element.

A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.

Piezoelectronic device with novel force amplification

A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Indirect readout FET

A circuit is provided. The circuit includes a ferroelectric tunneling junction ('FTJ') coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.

Symmetrically programmable resistive synapse for RPU using current-programmed single domain wall ferroelectric

According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.

Image sensor with analog sample and hold circuit control for analog neural networks

A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.

Three-terminal metastable symmetric zero-volt battery memristive device

Growing community of inventors

Yorktown Heights, NY, United States of America

Dennis Merton Newns