National Semiconductor Corporation

Dennis M Rose

David L Weigand

Gerard G Socci

Charles J Malek

Christian Volf Olgaard

Daniel E Fague

Steve Lo

A symmetrical correlator includes a shift register into which the bit pattern resulting from oversampling a received data signal are clocked using a sample clock. During each cycle of the sample clock, a first number of the bits contained in the shift register are provided to an enable circuit. The enable circuit compares these bits to a predetermined bit pattern and, in response to the correlation therebetween, generates an enabling signal. Also during each cycle of the sample clock, a plurality of bit pairs symmetrical about a predetermined bit position in the shift register are compared for logical equivalency in a plurality of associated logical equivalency circuits. Each of the logic equivalency circuits provides a signal indicative of the logic equivalency of its associated bit pair to an adder. When enabled, the adder sums the binary values provided thereto by the logical equivalency circuits to generate a signal SUM indicative of the degree of symmetry of the bit pattern contained in the shift register about the predetermined bit position for that clock cycle. A peak value for the signal SUM indicates the center of the bit interval of the data signal is precisely associated with the predetermined bit position of the shift register.

Symmetrical correlator

A technique is disclosed for allowing a seamless handover between base stations in a TDMA controller as a telephone handset is transported from one base station's area to another. The disclosed circuitry enables the TDMA controller to assess the quality of the handover before switching to the new base station. When it is determined that a handover operation is to commence, transmissions are made in the original slot time and a handover slot time within the same frame. Also during the same frame, data is received at two separate slot times. Only when it is determined that the data received in the handover slot time contains no transmission errors is the handover completed by then only transmitting on the handover slot transmit time and receiving on the handover slot receive time. In the preferred embodiment, it is determined whether the received data contains no transmission errors by detecting the CRC codes, the signal strength, and the existence of any invalid words.

Seamless handover in a cordless TDMA system

An apparatus for reducing the power consumed by, and the noise generated at the output of a charge pump which is part of a phase locked loop circuit. A reduction in the power consumed by the charge pump is achieved by synchronizing the powering up of the charge pump bias circuit to the state of the counters which control the timing of the signal which triggers a charge pump cycle. In this way current is supplied to the charge pump circuit only when needed for the operation of the pump. A reduction in the noise present at the output of the charge pump caused by the reloading of the counters while the pump is activated is achieved by loading a portion of the counter bits prior to activating the pump. A circuit detects when the counter is close to a value of zero and produces a signal which loads the most significant bits of the counter. When the counter reaches a value of zero, the remaining bits are loaded. This reduces the number of counter bits which are loaded while the pump circuit is active, thus reducing the switching noise present on the pump output.

Apparatus for reducing power consumption of device controlled by counter

A synchronization method for synchronizing a plurality of base stations in a TDMA communication system is disclosed. The synchronization topology may be via dedicated hardwire, via any DSL from the PSTN, or via an ad-hoc RF synchronization technique. Slots containing data are arranged in frames and these frames are transmitted to the base stations, and received from the base stations, by wireless telephone handsets. Each of the slots in a frame have a guard field comprising a plurality of guard bits. The base stations derive frame sync pulses via the received Unique Word correlation detect. These derived frame sync pulses are ultimately synchronized with frame sync signals received from the master base station. The slave base stations are maintained in synchronization with the master base station by using a phase locked loop (DPLL) which adds or deletes a final bit in the guard field of a frame to either advance or delay the frame sync pulse generated within the slave base station as necessary to maintain synchronization between the frame sync pulses generated by the slave base station and the frame sync pulses generated by the master base station.

Inter-base synchronization technique for a TDMA communication system

A ROM filter includes a number of ROMs, each of which is programmed to hold data relating to several pulse response curves during only a particular time interval. As data are read into the filter, data pertaining to a particular pulse response curve are addressed in each of the ROMs. The outputs of the ROMs are connected to an adder, which adds the data read from the ROMs and passes it through a digital-to-analog converter. In this arrangement, the ROMs are required to store only the data relating to the pulse response curves during a particular interval. These data are added together in real time in an adder which is external to the ROM. With this structure the area of the ROM can be significantly reduced, as compared with ROM filters in which the addition is programmed into the ROM.

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Sunnyvale, CA, United States of America

Dennis M Rose