Micro Component Technology, Inc.

Control Data Corporation

Dennis M Petrich

Gayle Russell Norberg

Robert J Wurscher

Thomas C Kelly

Jan B Wilstrup

Stanley L Gruenenwald

Christopher G Amick

Earl H Rideout

A transmission line connector for a contact set assembly for making contacts to contact elements of electrical devices, such as IC devices including DIPs and LCCs, affords a controlled impedance path between the contact elements of a device to be contacted and remote terminal ends of the respective transmission line conductors. The connector may be flexible or rigid. An actuating mechanism engages the connector adjacent the opposite end edges thereof for urging probe elements attached to the respective end terminals of the respective plurality of conductive lines into engagement with corresponding contact elements of the device to be contacted. A flexible transmission line connector permits rapid and continuous actuation of the actuating device between a normal disengaged position and an engaged position for making contact. The controlled impedance transmission line conductor is adaptable for providing contact to a wide range of device as to size and configuration, and as to number and location of contacts.

Transmission line connector and contact set assembly for test site

An improved delay lock loop which has first and second means (32, 34) for generating a voltage ramp, the first ramp generator (32) providing a train of ramped inputs to first time delay means (38) responsive to a first input pulse train and the second ramp generator (34) providing a train of ramped inputs to a second time delay means (40) responsive to a second input pulse train. The ramp generators (32, 34) provide a highly linear voltage ramp. First and second retrace means (36A, 36B) are connected to the first and second ramp generators (32, 34) respectively and act to limit the ramps to a certain voltage, commanding the ramp generators (32, 34) to return to a reference voltage to await the succeeding input pulse edge transition. A further improvement comprises range switch means (44) that function to selectively control the maximum range of time delay which the delay lock loop is able to sense. This permits selecting a greater or lesser range of time which the delay in time intervals between the edge transitions of the pulses in the first and second input pulse in the first and second input pulse trains can have and still be measured. Additionally, calibrator means (26) are incorporated which provide signals to the delay lock loop and ancillary electronics to determine the delay inherent in these devices. This delay is stored and subtracted from the delay determined by the delay lock loop to increase the accuracy. The calibrator (26) additionally very accurately determines the voltage difference between the voltage representing zero volts on the ramp and the voltage representing full scale on the ramp to very accurately determine the voltage span representative of the selected range.

AC parametric circuit having adjustable delay lock loop

An improved test system for performing DC and AC parametric and dynamic functional testing of multi-terminal integrated circuits is described. All of the circuitry for producing and responding to D.C. and high-integrity stimulus and response test signals is located within a Test Head module sized for use in close proximity of the device under test. A high-integrity bus in the Test Head interconnects the high-integrity producing and handling circuits, with inexpensive connectors and batch-fabricated printed circuit board techniques. A Controller provides digital test commands for energizing the test signal producing cirucits within the Test Head and for evaluating the test results. The control and measurement signals passing between the Controller and the Test Module require no special conductor implementation techniques. A unique detachable, modularized bussing scheme between the Controller and Test Head and within the Test Head enables the test system to be manufactured at minimum cost, while maximizing reliability, signal integrity and manufacturing repeatability from system to system and enables rapid replacement and interchangability of test circuits and functional capabilities without sacrificing the quality of bus structure that carries the high integrity signals.

Integrated circuit test apparatus test head

A delay lock loop has a fixed delay element, means for detecting the edge transitions of pulses, analog or digital feedback means related to the timing differences between the edge transitions of a pair of pulses and a variable delay means responsive to the feedback means for adjusting the timing differences between a pair of pulses in response to the feedback signals. In the analog embodiment, the feedback may be a voltage related feedback with a varying voltage controlling a voltage responsive variable delay means. In the digital embodiment, the feedback means may use a counter responsive to signals from an edge detecting flip-flop and the counter may control a programmable delay means.

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Wayzata, MN, United States of America

Dennis M Petrich